DP83825I: Slave Mode Oscillator Layout

In this case, the PHY and MAC communicate one-to-one. The clock line is also one-to-one.

The pattern length is about 60 mm.

The board is 8 layers, allowing for impedance matching.

I would like to keep costs as low as possible.

Is a clock buffer necessary?

Hi,

I would this recommend to use a clock buffer if it is possible. This would provide a clock to the PHY and the MAC as clean as possible. My biggest concern with sharing the same clock between the PHY and the MAC is the clock signal integrity which could impact PHY's ability to link up or packet loss/corruption due to the poor clock signal quality.

Thanks

David

When using a clock buffer, is the following configuration OK? The oscillator is near the PHY. The clock buffer is near the MAC. Also, other ICs would be fine, but are there any layout documents for RMII slave mode (refclk output from an external oscillator)? I'd like to use an evaluation board or something similar as reference.

Hi,

The 50 MHz Oscillator will feed into the clock buffer, and the multiple buffer output will feed to the PHY and the MAC.

iIf MAC has a 50MHz CLK output, you could feed it into DP83825 XI in RMII slave mode. You could also configure the PHY into RMII master mode, and then feed PHY CLKOUT into MAC REFCLK input. Both approach would not require a clock buffer. 

Thanks

David 

Thank you for your reply.
By the way, is the BIST function effective for verifying communication between PHY and MAC?

By the way, the MAC uses AM4378.