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DP83869HM: 2-Level Strapping Revision

Brendan Toy
Prodigy 160 points
Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Tool/software:

To whom it may concern - 

Noticed that the DP83869 Datasheet Revision from C to D, updated the "4-Level Strapping Mode 0 Rlo recommendation changed from 2.49k to OPEN". I assume this is referring to Table 10 2-Level Strap Resistor Ratio instead of the 4-level Strap, because Mode 0 Rlo is changed from 2.49k to OPEN.

Revision C:

Revision D:

With this in mind, we followed datasheet revision C (with Rlo = 2.49k for 2-level application). Few questions:

- What is the reason for this strap resistor change?

- Do you recommend we do no install the Rlo to align with Revision D?

- Since JTAG_TDO is a multi-use pin, how should we strap it if we plan to use JTAG boundary scan?

Thanks,

Brendan

  • 0
    TI__Mastermind 30630 points

    Hi Brendan,

    We updated that Rlo value because DP83869 has an internal pulldown on 2 level strap pins.

    The internal pulldown will pull these straps low if no strapping resistors are used, so Rlo is not a requirement. It is ok to keep Rlo, however it would save BOM cost to remove it, hence why we made this change.

    Brendan Toy said:
    - Since JTAG_TDO is a multi-use pin, how should we strap it if we plan to use JTAG boundary scan?

    Any strap resistor should be weak enough such that it does not interfere with JTAG operation. This would be similar to how the MAC interface data pins are also strap settings.

    I hope this helps, let me know if you have further questions.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Prodigy 160 points

    Hi Shane,

    I see. so if that is true, I don't see how Vmax for Mode 0 can be anywhere close to 0.18 x VDDIO, unless there is also a pull up internally. I found this image from the forum here:  DP83867E: Strap Configuration Status Register (0x6e) reset?

    To me, it looks like there is some comparator during power up and reset, then switches to the buffer during normal operation.

    Additionally, based off of Figure 6-1 Power Up Timing and T1-T3 in 6.6 Timing requirement, is it saying that reset shall be held low for minimum of 200ms after VDDIO is high to allow the hardware strap is read properly?

  • 0 in reply to Brendan Toy
    TI__Mastermind 30630 points

    Hi Brendan,

    Brendan Toy said:
    I don't see how Vmax for Mode 0 can be anywhere close to 0.18 x VDDIO, unless there is also a pull up internally.

    Vmax is the maximum voltage that can be supplied on the strap pin that will latch in as mode 0. DP83869 does not present this voltage from an internal pullup. In reality I would expect a voltage reading at or near GND if no external pullup is connected during the strap's latch in window.

    • I'm not sure where that image is coming from, as it looks to have been made within the linked E2E post. There should not be an internal pullup during the strap latch-in phase. I would defer to the datasheet's figure 7-15 for the internal strap pulldown.
    Brendan Toy said:
    is it saying that reset shall be held low for minimum of 200ms after VDDIO is high to allow the hardware strap is read properly?

    Reset should be held low for 200ms so the PHY can initialize and stabilize correctly. My understanding is that the strap pins are read immediately after reset is allowed to rise. Essentially the straps should not be latched in if the PHY is held in reset. In this context I believe T3 reflects the strap latch-in point when reset is released at 200ms (T1). 

    • In short the 200ms is not for the straps to be read, it is for the PHY to stabilize after power up. The straps should be read after reset is de-asserted. I will discuss this internally to be certain, and will update on this thread if any correction is needed.

    Best,

    Shane