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Original question:

TMUXHS4212: Cascaded implementation

TMUXHS4212: Cascaded implementation

Yasar Maheen Seenath
Prodigy 190 points
Part Number: TMUXHS4212


Tool/software:

Hello Team,

Could you please help to review the schematic of the cascaded implementation which was communicated previously with Blok diagram?

TMUXHS4212_cascaded_Implementation.pdf

Kindly confirm the requirement of coupling caps on Tx side of both MUXes.

But we got a very low bandwidth of ~100Mbps, when performing below test.

We performed both sequential and random read/write tests using fio with direct I/O.

The device used to test the interface was Sabrent 512GB Rocket NVMe PCIe M.2 2242 SSD.

Test Setup Summary
--------------------------
Tool: fio with libaio engine and direct I/O
Block Sizes: 1M for sequential, 4k for random
Device: Sabrent 512GB Rocket NVMe PCIe M.2 2242 SSD
Mount Point: /mnt/PCIe

Please help.

  • 0
    TI__Intellectual 1370 points

    Hi Yasar,

    1. The coupling capacitors you've selected appear appropriate for this high-speed application
    2. We do have a FAQ on multiplexer cascading effects, which provides information on bandwidth degradation in such configurations. Typically, when doing cascading you will have double the losses.
    3. While your schematic design does look good, I noticed you have unconnected pins on PCIe CLK MUX2 and PCIe MUX1. This may be fine in low-frequency environments, but for highspeed you would want to terminate them to avoid potential noise coupling and signal integrity issues.

    Thank you,

    Arya 

  • 0 in reply to Arya Hussein
    Prodigy 190 points

    Hi Arya,

    Thanks for the feedback.

    So, what is the recommended unused pin termination here?

  • 0 in reply to Yasar Maheen Seenath
    TI__Intellectual 1370 points

    Hi Yasar,

    We recommend to tie these unused inputs to GND through a termination resistor (normally a 50ohm resistor).

    Thank you,

    Arya

  • 0 in reply to Yasar Maheen Seenath
    Prodigy 190 points

    Hello Arya,

    I have a follow-up question here.

    Did you referred to analog bandwidth (-3dB roll off) or quantized digital bandwidth of the interface?
    Because these two are not the same with regard to cascaded multiplexers and the term “bandwidth”.

    Could you please clarify this?

    Also, do you think that any SW optimization from SoC/MUX side will help in improved bandwidth in cascaded implementation?

  • 0 in reply to Yasar Maheen Seenath
    TI__Intellectual 1370 points

    Hi Yasar,

    Yes, it is referring to the -3 dB roll-off point. Physical limitations are the main component here.

    The bandwidth limitations described are a direct result of the physical properties of the multiplexers. As you cascade them, the total On-Resistance and On-Capacitance of the signal path increase. This creates a higher-order low-pass filter, which inherently has a lower cutoff frequency (less bandwidth). So, I don't believe optimizing software will help improve physical limitations.

    Thank you,
    Arya