Part Number: DP83822I
Tool/software:
Greetings,
We have a new HW design which interfaces the DP83822 10/100 Phy to an IMX93 over
RGMII, and are having issues getting a link to one of our older products.
Our older ethernet device has an optical interface, and runs at 10 Mbps, full duplex,
asym. pause flow control, and auto-negotation disabled.
What we have done so far:
Checked all pin muxing and the IMX93, looks good.
Can read/write the standard IEEE MDIO registers (0x00-0x1F)
Can read/write the the MDIO extended registers.
Check the power up sequence, looks good.
Checked the Linux driver reset GPIO operation, looks good.
Verified that the PWRDN signal is high, not power down mode.
Scoped the RGMII signals they all look good, with one exception the RGMII_TX_CLK
Ran some loopback tests.
I use 10 Mbps/FD/AN-disabled for all loopback tests, plus Auto-MDI-X is disabled
Using register 0x16, I can get the PCS loopback, and the Analog loopback to work.
Using register 0x16, I cannot get the Digital loopback to work? Link does not come up?
Using just 0x00 (BMCR) I cannot get MII Loopback to work? Link does not come up? Am I doing MII loopback correctly?
Here is the sequence of MDIO operations I use to setup a test.
0x1F <= 0x8000
0x00 <= 0x0100
0x04 <= 0x0061
0x16 <= 0x000X ## type of loopback
Anyways we have tried to get the new HW and the old HW to link up over a short distance (centimeters),
and we get intermitent link bouncing events, where the link stays up for less than a second, then goes
down for many seconds.
We think that they TX clock is the problem, as when we scoped it, it was not a square wave, picture attached.
We then tried several pin pad setttings, at the IMX93, to see if we had a bad pad configuration value
for the TX clock pin. No luck. We are using a value 0x51E for the RGMII pins, which a lot of
RGMII device trees in the IMX8/IMX9 family use successfully.
We then cut the etc on our board, and then saw that the IMX93 side had a perfect 2.5 Mhz square wave.
Re-connecT the etch, bad clock.
So, we are thinking that somehow the 83822 is also driving the TX clock pin?
Can this be? Usually an input pin to the 83822? Correct?
One thing that we are not doing, is strapping the DP83822.
I see that most designs make use of the HW strapping, but for some reason, our HW designer
chosen not to?
[ 5951.608247] imx-dwmac 428a0000.ethernet eth0: Link is Up - 10Mbps/Full - flow control off
[ 5952.630991] imx-dwmac 428a0000.ethernet eth0: Link is Down
[ 5969.016239] imx-dwmac 428a0000.ethernet eth0: Link is Up - 10Mbps/Full - flow control off
[ 5970.038965] imx-dwmac 428a0000.ethernet eth0: Link is Down
[ 6044.792263] imx-dwmac 428a0000.ethernet eth0: Link is Up - 10Mbps/Full - flow control off
[ 6045.815034] imx-dwmac 428a0000.ethernet eth0: Link is Down
root@draeger-osm-sf-imx93:~# ./phytool dump eth0/1/1
MII [00]: 0x0100
MII [01]: 0x7849
MII [02]: 0x2000
MII [03]: 0xA240
MII [04]: 0x0C61
MII [05]: 0x0000
MII [06]: 0x0004
MII [07]: 0x2001
MII [08]: 0x0000
MII [09]: 0x0000
MII [0A]: 0x0100
MII [0B]: 0x1000
MII [0C]: 0x0000
MII [0D]: 0x4007
MII [0E]: 0x0000
MII [0F]: 0x0000
MII [10]: 0x0006
MII [11]: 0x0108
MII [12]: 0x2000
MII [13]: 0x0800
MII [14]: 0x0000
MII [15]: 0x0000
MII [16]: 0x0100
MII [17]: 0x0049
MII [18]: 0x0400
MII [19]: 0xA021
MII [1A]: 0x0000
MII [1B]: 0x007D
MII [1C]: 0x05EE
MII [1D]: 0x0000
MII [1E]: 0x0002
MII [1F]: 0x0000
Summary:
Link bouncing at 10 Mpbs, FD, !AN
Some loopbacks work, some do not?
Strange RGMII TX clock
Any advice would be appreciated!
Thanks
Ken Carlson
