Other Parts Discussed in Thread: DP83620, DP83869
Hi,
We're migrating a custom PCB design from DP83620 to DP83869, in both cases using fiber mode, with the intent of being able to admit both 100 and 1000 SFPs, having compatibility with the old design.
The original design with DP83620 worked perfectly, but we are now incapable of having the new interface to work, either with the old 100mbps SFP or with a new 1000 mbps SFP.
Attached is the meaningful part of the schematic: ethernet.pdf
SFP cage and DP83869 itself. The PHY is connected to an Artix 7 FPGA, which fits the AXI 1G/2.5G Ethernet Subsystem IP core from Xilinx. In the old board, this core was set in MII mode, now it is configured in RGMII mode, but that is the only difference.
Also attached are Device Tree entries. The only difference between old and new design is the change of phy-mode from "mii" to "rgmii" and the PHY address that has changed from 1 in the old design to 0 in the new one (although we'll probably change that default to 1 also, so that's one less thing to worry about).
Sadly, we weren't able to route dedicated SFP pins such as presence or LOS, but that was the case also with the old design, in which we didn't rely on these pins for anything. We've tried with the old 100mbps SFP changing ti,op-mode to RGMII_100_BASE option, but in no case will the system establish connection.
The kernel does see the SFP and does seem to communicate with the PHY but no connection exists. What may be going on?
This is the kernel outpout with DP83869_RGMII_100_BASE and the old 100mbps SFP connected:
sfp amba_pl:sfp: Host maximum power 1.0Wsfp amba_pl:sfp: No tx_disable pin: SFP modules will always be emitting.sfp amba_pl:sfp: module OEM SFP-5000-RJ45A rev A sn HLY23C0619012 dc 230619
xilinx_axienet 40c00000.ethernet eth0: PHY [axienet-40c00000:00] driver [TI DP83869] (irq=POLL)xilinx_axienet 40c00000.ethernet eth0: configuring for phy/rgmii link mode
# ethtool eth0Settings for eth0: Supported ports: [ TP MII FIBRE ] Supported link modes: 100baseFX/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: Not reported Advertised pause frame use: Symmetric Receive-only Advertised auto-negotiation: No Advertised FEC modes: Not reported Speed: Unknown! Duplex: Unknown! (255) Port: FIBRE PHYAD: 0 Transceiver: external Auto-negotiation: off Link detected: no
Replacing the old SFP with the new one and ti,op-mode to DP83869_RGMII_100_BASE, makes this output:
sfp amba_pl:sfp: Host maximum power 1.0W
sfp amba_pl:sfp: No tx_disable pin: SFP modules will always be emitting.
sfp amba_pl:sfp: module OEM SFP-GE-T rev sn CSGE1NC2812 dc 23122701
# ethtool eth0Settings for eth0: Supported ports: [ TP MII FIBRE ] Supported link modes: 10baseT/Full 1000baseX/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: Yes Supported FEC modes: Not reported Advertised link modes: Not reported Advertised pause frame use: Symmetric Receive-only Advertised auto-negotiation: No Advertised FEC modes: Not reported Speed: 10Mb/s Duplex: Half Port: FIBRE PHYAD: 0 Transceiver: external Auto-negotiation: off Link detected: no
This output is a bit confusing, since it lists both 10baseT and 1000baseX as link modes, with 10Mb as speed. I manually change it to 1000
# ethtool -s eth0 speed 1000
# ethtool eth0|grep Speed Speed: 1000Mb/s
But nothing useful will come out of it.
What could be going on?
sfp0: sfp {
compatible = "sff,sfp";
i2c-bus = <&axi_iic_0>;
};
axi_ethernet_0_dma: dma@41e00000 {
compatible = "notxlnx,axi-dma-1.00.a";
#dma-cells = <1>;
reg = <0x41e00000 0x10000>;
interrupt-parent = <µblaze_0_axi_intc>;
interrupts = <7 8>;
xlnx,addrwidth = <32>; // Tamaño de dirección en bits
xlnx,datawidth = <32>;
xlnx,include-sg;
xlnx,sg-length-width = <16>;
xlnx,include-dre = <1>;
xlnx,axistream-connected = <1>;
xlnx,irq-delay = <0>;
dma-channels = <2>;
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk";
clocks = <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>;
dma-channel@41e00000 {
compatible = "xlnx,axi-dma-mm2s-channel";
xlnx,include-dre = <1>;
interrupts = <7>;
xlnx,datawidth = <32>;
};
dma-channel@41e00030 {
compatible = "xlnx,axi-dma-s2mm-channel";
xlnx,include-dre = <1>;
interrupts = <8>;
xlnx,datawidth = <32>;
};
};
axi_ethernet_eth: ethernet@40c00000 {
compatible = "xlnx,axi-ethernet-1.00.a";
reg = <0x40c00000 0x40000>;
phy-handle = <&phy1>;
interrupt-parent = <µblaze_0_axi_intc>;
interrupts = <3>;
phy-mode = "rgmii";
xlnx,rxmem = <0x1000>;
max-speed = <100000>;
xlnx,txcsum = <0x2>;
xlnx,rxcsum = <0x2>;
clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
clocks = <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>, <&clk_bus_0>;
axistream-connected = <&axi_ethernet_0_dma>;
/* dmas = <&axi_ethernet_0_dma 0>, <&axi_ethernet_0_dma 1>; */
dma-names = "tx_chan0", "rx_chan0";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@0 {
compatible = "ethernet-phy-id2000.a0f1";
device_type = "ethernet-phy";
reg = <0>;
sfp = <&sfp0>;
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
ti,op-mode =
<DP83869_RGMII_1000_BASE>;
};
};
};