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Original question:

SN65DSI86: question about SN65DSI86

SN65DSI86: Max resolution supported in 4 lanes mode

fd
Intellectual 725 points
Part Number: SN65DSI86


According to https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1497010/sn65dsi86-question-about-sn65dsi86/5795752 the supported resolution and video mode of the SN65DSI86 does not depend on the amount of lane, but just on the available bandwidth.

  1. Can you confirm that it should be possible to have 4k@30 with 18BPP on 4 lanes MIPI DSI? 
  2. Is there any limitation in the Linux kernel drivers/gpu/drm/bridge/ti-sn65dsi86.c driver to support the configuration described in point 1?

 

  • 0
    TI__Mastermind 25890 points

    Hello,

    The DSI86 is a DSI to eDP/DP bridge. The video bandwidth that can be transmitted depends on both the input and output interfaces.

    For the DSI input, it can support up to 750 MHz clock frequency and 1.5 Gbps per lane. Over 8 lanes, dual DSI ports, it can support a maximum of 12 Gbps video input.

    The DP output video can support 1, 2 or 4 lanes at different lane rates as mentioned on the front page.




    1. For the full video bandwidth, it would help if you shared the pixel clock rate of the 4K video, since the blanking can vary.

    Assuming, that the pixel clock rate = Htotal * Vtotal * fps = 4400 pixels * 2250 lines * 30 fps = 297 MHz. 
    Then the video bandwidth = PCLK * bpp - 297 MHz * 18 bpp = 5.346 Gbps

    This can be supported with 4 lanes because each data lane can support up to 1.5 Gbps.

    For the detailed calculations, please refer to this app note section 3: https://www.ti.com/lit/ab/slla425/slla425.pdf

    2. The DSI86 programming tools are shared here: [FAQ] SN65DSI8x Programming Tools

    The timings/ resolution would need to be entered for your specific display application.

    Best regards,
    Ikram