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SN65DSI84: MIPI/LVDS Issue

Fabio Soriano
Expert 4440 points
Part Number: SN65DSI84


I open a new thread here where we can discuss directly with the customer:

The reference is the image below:

  • Line time sync-to-sync 26.880 us
  • Data burst time based on actual DSI Ch*CLK and data throughput 6.504 us

dinema.ref.png

In the Texas instruments example the lvds and mipi timing timings are quite different and in contradiction with the responses so far, in which the two timings must be accurate and corresponding. 

d1.png

d2.png

From which follow the timelines reported above and indicated in the first email of this second series.

Is the example I'm referring to, taken from the application note, clear to you?

Thank you and have a good day.

 

Regards,

Fabio

  • 0
    TI__Mastermind 25120 points

    Hi Fabio,

    The example in the app note for 1024x600 is not accurately showing the line time requirement here. This E2E shows an example for the line time: [FAQ] SN65DSI84: Line Time with the SN65DSI84

    You can use this resolution guide to calculate the inputs required:[FAQ] SN65DSI84: SN65DSI83, SN65DSI84, and SN65DSI85 resolution guide

    Fabio Soriano said:
    • Line time sync-to-sync 26.880 us
    • Data burst time based on actual DSI Ch*CLK and data throughput 6.504 us

    The Data burst time is different from the line time sync to sync.



    Example:

    The main consideration for the DSI84 will be that the LVDS output is split for dual LVDS channels, and the LVDS clock will be half the pixel clock rate(as shown in the resolution guide).

    So please program the DSI input resolutions accordingly. Here is another example from E2E: RE: SN65DSI83: Support
    Note how the LVDS horizontal timings are half the DSI inputs, since dual LVDS output is used for DSI84:




    If you use the line time E2E example, then you will find that the line times match for DSI input and LVDS output.


    To summarize, please program the DSI input resolution (Horizontal/vertical total, active, blankings) to match the panel LVDS requirements. And for the DSI84 with dual LVDS, the horizontal timings will be split between the LVDS channels (as also noted in the DSI Tuner GUI).


    Is there any issue with this? Can the DSI source in the customer's system not be programmed for exact display timings?


    Best regards,
    Ikram