SN65LVDS2: Input termination of SN65LVDS2

Hi TI team,

My applicatioin needs a differential to LVCMOS/LVTTL conveter to convert a 78.125Mhz differential clock to a 78.125Mhz single end clock. I plan to do ac-coupling and external bias as below. Could you help check if it is feasible? Thank you!

Differential clock output characteristic

Schematic

Thanks,

YW