TCAN4550: Tclqv Value

Hi Mike,

The TCAN4550 uses different timing parameter names, but you can see the figures and specifications table to determine the timing requirements.

If I understand the question correctly, the question is about how long the delay is between the clock transition and the time when the data bit is stable enough to sample.  

Generally the SPI Output data is changed on the Falling Edge of the SCLK and sampled on the rising edge.  However, the time between the falling clock edge and when the output data is valid is a maximum of 20ns (tsov). The signal rise/fall time could be added to this for additional margin if the data is being sampled through other means.

Regards,

Jonathan