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Original question:

DP83826I: Function of PHYCR (Offset = 19h). Bit 5

DP83826I: DP83826(A)I with EtherCat an MI link detection

Thomas Donner
Prodigy 160 points

Part Number: DP83826I

If the DP83826(A) is used with the Beckhoff EtherCat IP-Core the Beckhoff PHY Addendum

(https://download.beckhoff.com/download/document/io/ethercat-development-products/an_phy_selection_guidev3.2.pdf)

Beckhoff wants that MI link detection is disabled if IP-Core 3.xx Version is used, because this Version is making write accesses to PHY register 9.

What exactly happens if IP-Core 3.xx with activated MI link detection is used with DP83826(A)I (enhanced mode). Which bits are changed in this Register?

Kind Regards

Thomas

  • 0
    TI__Mastermind 34205 points

    Hi Thomas,

    If MI link detection and configuration is enabled with DP83826A on an older IP core, it would likely attempt to configure DP83826A through register 9 and poll this register for the link status.

    The issue here is that register 9 on DP83826A is not for configuring the PHY address or link status. Register 9 has a few miscellaneous configuration options that may be altered by the IP core if your controller has active MI link detection/configuration.

    I'm unsure of what specific register writes would affect 0x9 as this is not an intended use case for DP83826A. I recommend disabling MI link configuration and detection as noted in the PHY selection guide you've linked:

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Prodigy 160 points

    Hi im also in contact wih the ETG.

    From the ETG I get this information:

    Hello Mr. Donner,

    I have clarified the exact background of the function in EtherCAT IP core version 3 and the reason for the note in the PHY Selection Guide with the developers.

    EtherCAT IP Core V3.0.10 writes either 0x0000 (port 0) or 0x0400 (ports 1-3) to register 9.

    From EtherCAT IP core V4.0.0 onwards, the ESC only writes to register 9 for Gigabit PHYs.

    All 16 bits are always written.

    The note in the datasheet stems from experiences with TI's TLK1xx PHYs, which then do not function normally.

    These PHYs have undocumented writable bits that are set to 1 by default.

    The note was then extended to all PHYs that use register 9 but do not have a standard assignment – ​​such as the DP83826.

    According to the datasheet, the DP83826 should function normally with the values ​​0x0000 and 0x0400. However, a reserved bit is written (bit 10, which the datasheet states should not be writable), and bit 5 is cleared (Robust Auto-MDIX). This should be acceptable, though.

    However, we cannot release this configuration because datasheets can be incomplete (based on our experience with, among others, the aforementioned TLK1xx PHYs from TI).

    On the other hand, MI link detection & configuration can simply be disabled on a 100 Mbit PHY like the DP83826 – the primary purpose of this function is to prevent 1000 Mbit links with Gigabit PHYs.

    I hope this answers the question about the impact – we cannot rule out interactions, including those caused by potentially undocumented bits.


    However, we cannot rule out other possibilities. Since this function is not strictly necessary for the operation of 100 Mbit PHYs, we recommend disabling MI link detection&configuration.

    So the only bit in the Register of the DP83826 (not A)  who are set to 1 is Bit 10 who is dokumentet as read only.


    This person didn´t also say anything about read acesses of the IP-Core.


    So an write of the IP Core (V3.xx activated MI link detection) shoudn´t change anything in this register. Do you agree?


    Kind regards
    Thomas Donner



  • +1 in reply to Thomas Donner
    TI__Mastermind 34205 points

    Hi Thomas,

    I agree the written values of 0x0000 and 0x0400 should only affect the default value of robust Auto-MDIX. If these are the only register writes possible, and you are not concerned with auto-MDIX, then this is may be ok from the PHY functionality perspective.

    For my own understanding, is there a reason you need to keep MI link detection and configuration active in your design? This should be ok to disable in 100M PHYs per the ETG's reply.

    Thomas Donner said:
    On the other hand, MI link detection & configuration can simply be disabled on a 100 Mbit PHY like the DP83826 – the primary purpose of this function is to prevent 1000 Mbit links with Gigabit PHYs.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Prodigy 160 points

    We had to do a redesign of 2 PCBs because the old PHY-ICs has a last time buy.
    On these two plattform we offer 3 different Ethernet protocols. The protocoll decission is done by the FW the user is loading down.

    If make bigger HW changes in the Plattform (perhaps Pin changes) we hat do Prevent that the user can load down the wrong FW in the plattform.
    Soo we hat to generate new Firmware build targets and support them over years (old and new versions * Number of protokolls)

    Because we didn´t made any pin changes in the Design with the PHY change and two o the protokoll stacks already know the DP83826, this Register issue can be the only reson why we had to or don´t had to generat 3 new Firmware Targets or not and support them over the next 10 years.

    This is why i fighting so had for informations.

    kind regards

    Thomas



  • 0 in reply to Thomas Donner
    TI__Mastermind 34205 points

    Thanks for the context Thomas.

    Let me know if you have any more questions on this device or if you need help designing DP83826(A) into your system.

    Best,

    Shane