DP83826AE: Strapping DP83826AE for EtherCAT applications

Part Number: DP83826AE

The strap configuration according to datasheet mentiones that "For EtherCAT applications or applications with Fast link drop enabled and expect to handle Baseline wander packets, recommend disable signal energy detect, which can be done by setting Strap8 "

1) This implies from flowchart Strap 1=0(MII, odd nibble disable), strap7(FLD enable)=1 (This is clear)

2) Now application note schematic implements 1* strapping along with Strap8=1(go to strap 11) and strap 11=1(disable error-counter FLD)

This doesnt match with the table provided in application note for strapping where strap8 is suggested to be set to 0(Energy signal enable)

image.png

Can you confirm what should be the strapping for EtherCAT with FLD enable, Energy detect disable wrt Strap 8.

Also is the configuration given in application note for Ethercat implementation makes sure FLD is enabled? becaure initially on Strap 7 we enable FLD but again in strap 11 it is mentioned FLD is disabled

Is the following flowchart correct for ethercat implementation for DP83826AE
image.png

  • Hi,
    FLD and signal energy detect enable are the same thing. 
    One of the threshold that triggers FLD is signal energy detect and this threshold is what we recommend for our customers to use for enhanced EMC performance our device produces. 

    The flowchart is wrong. You need to have strap8 low and strap 11 high so it triggers FLD enable for signal energy detect. 

    Best,
    J

  • The schematics given in the DP83826AE application note gives a different strap configuration for strap 8 and 11. I am mainly looking for EtherCAT application using this IC

    Can you kindly confirm the strapping

  • Please ensure FLD is enabled (RX_D2 LOW) and signal energy detect enabled (RX_CLK HIGH) for EtherCAT application. 

    Best,
    J

  • In datasheet it mentions that for ethercat applications, Signal energy detect needs to be disabled. This is in contradiction to what you are suggesting. Can you kindly let us know which is the correct source and resolve this ambiguity

    If it is okay, can we have a teams call on to resolve this issue?

  • Hi, 

    That statement only applies when you expect the PHY to handle baseline wander packets during EtherCAT application. This is not true for every EtherCAT application. Otherwise, for better EMC performance, I recommend FLD is enabled (RX_D2 LOW) and signal energy detect enabled (RX_CLK HIGH) for EtherCAT application. For baseline EMC performance, you can refer to DP83826 D/S. 

    Best,
    J

  • We are interested in EtherCAT applications with no signal energy detect since it might cause baseline wander issues (in alignment with the discussion in the thread DP83826E: signal energy detect disable - Interface forum - Interface - TI E2E support forums for ethercat in MII mode)

    Beckhoff suggests "Baseline wander should be compensated and the PHYs should cope with the ANSI X3.263 DDJ test pattern" for etherCAT applications

    Hence we want to proceed with option of disabling signal energy detect for FLD and follow the following strapping

    Starp1=0, Strap7=1, Strap8=1 and strap11=0 ( 4th FLD strap option)

    Can you kindly confirm if we can go ahead with this strapping option

  • Hi,

    In that case, yes, your strapping option works. However, please note that baseline wander issue should not be observed in most cases since there will always be a packet transitioning in Ethernet. 

    Best,
    J