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Original question:

TCAN1042-Q1: The output is low for 2ms after waking up

TCAN1042HGV: TCAN1042HGVD on an ISO CAN bus puts out Frame Stuffing Error on power up

Eric Hanisch
Prodigy 30 points

Part Number: TCAN1042HGV
Other Parts Discussed in Thread: TCAN1042HV

We are using the TCAN1042HGVD parts on an ISO CAN bus with split power 5V and 3V3 for VIO.  On a CAN analyzer right at power up we are getting a Frame error stuffing error.

A couple questions:

1.) Are there any VCC vs VIO power sequencing requirements?  On our board they both follow each other obviously and 3V3 VIO comes up just before 5V fully.

 

2.)  Have seen other forum issues related to the TX dominatnt timeout which I believe might be the cause attaching some scope plots of our ISO CAN CAN_P data, EN, TXD, and RXD.  These would all be behind a ADI ADUM142E isolator before getting to the NXP processor as well.  So am leaning towards it could similar to the reported 2ms after waking up issue  already in the forum. The comment about digital isolator I am guessing might be our issue here:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1300652/tcan1042-q1-the-output-is-low-for-2ms-after-waking-up?tisearch=e2e-sitesearch&keymatch=TCAN1042#

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1301997/tcan1042-q1-tx-dominant-timeout?tisearch=e2e-sitesearch&keymatch=TCAN1042#

ISOCAN_EN_CANP_RXD_TXD.jpg

ISOCAN_TTLwithPWR.jpgISO_CAN0_with_TTL.jpg

  • 0
    TI__Guru* 77652 points

    Hi Eric,

    The behavior seems to line up similar with TXD being low (dominant) during power-up, before the MCU is driving valid levels. Hence, when TXD is held dominant long enough, the TXD dominant timeout kicks, releases the bus and that dominant “blob” right at bring-up could look like a stuffing / frame error to a CAN analyzer.

    1. No specific sequencing required. However, under-voltage conditions / thresholds should be met for normal mode as shown in table 9-2 of the data sheet.

    2. Yes if a case where the isolator output defaults low or glitches low while the supplies are ramping, the transceiver may see TXD as low and drive dominant until DTO expires, then releases the bus. This “dominant pulse” could then easily trigger a CAN analyzer to report frame / stuffing errors right at startup and may include a pull-up to confirm (or ensure the isolator defaults TXD high at startup. May also choose to hold the device in standby mode during the ramp, boot the MCU and enter normal mode after the rails / isolator settles), thanks.

    Best Regards,

    Michael.

  • 0
    Prodigy 30 points

    Michael,

    Thanks and yes i think i am narrowing down to 3 things/issues:

    1.  Yes the TXD low during power up is triggering that TXD dominant timeout.

    2.  On our board the ADUM142E is fault level low so I believe that is also pulling TXD low in this short time frame.

    3.  On our board our NXP processor I/O CAN TTL pin is pulling the TXD line low for a short period on power up as well.

    This screenshot I have bypassed the ADUM142E (removed it and wire jumped across on the PCB) and I added a 10k pull-up on the TXD pin.  I dont get the frame stuffing error at boot.  Do see it on power shut down but not concerned about that yet or at all.

  • +1 in reply to Eric Hanisch
    TI__Guru* 77652 points

    Hi Eric,

    Thanks for double confirming as your test seem to confirm the stuffing error is caused by TXD being pulled low during power-up (from the isolator default-low state and / or MCU pin behavior), driving the bus dominant long enough to trigger TXD dominant timeout and creating a non-valid CAN waveform seen by the analyzer.

    Hence, adding the pull-up on TXD at the transceiver side and ensuring the isolator / MCU do not force TXD low during ramp prevents the issue (startup TXD biasing); rather than a power sequencing between VCC and VIO. Please do let us know if any additional concerns, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 30 points

    Just to close up this issue it turns the issue was 3 fold:

    1.)  Our isolated design needs to change to the the ADUM142E1's to fail-safe high when a VDDI is unpowered.  We had the 142E0's which fault-low at power on.

    2.) We need pull-ups on TXD both sides of the ADUM142E1's.  We dont have pull-ups on TXD/RXD/EN.  Dont see any mention of internal pull-ups in the TCAN1042HV part some other transceivers mention internals.  Still would need them on the other side of the isolators anyway.    

    3.)  Probably not required but what i have tested and think will end up doing is a FET inverter off our CAN_EN_B on both sides of isolator and then into the TTL data ADUM142E1  VEN's as well so a RST takes the whole path up/down isolator and transceiver 

    With all the above applied we do get a nice clean power up on TTL CAN RXD/TXD into the CAN1042