Part Number: TCA9803
Other Parts Discussed in Thread: TCA9617B, TCA39306
Hello,
We are evaluating the TCA9803 and would like to confirm whether the following configuration is supported.
As shown in the attached figure, a CPU is connected to the A-side of the TCA9803, and multiple I2C slave devices are connected in parallel on the B-side (multi-drop configuration).

We would like to confirm the following points based on the TCA9803 datasheet:
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Is it acceptable to connect multiple I2C slave devices on the B-side of a single TCA9803, as long as each slave has a unique I2C address?
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If this configuration is supported, are there any specific limitations or constraints we should be aware of, such as:
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Maximum total bus capacitance on the B-side
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I2C speed limitations (e.g., 100 kHz / 400 kHz)
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Restrictions regarding external pull-up resistors or other current sources on the B-side
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Are there any recommended design guidelines or common pitfalls when using the TCA9803 in this type of multi-slave B-side configuration?
The intention is to use the TCA9803 as a level-translating I2C buffer, with a single master on the A-side and multiple standard I2C slave devices on the B-side.
Thank you for your support.
Best regards,
Conor