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DP83867IS: Errors with Ethernet qualification

Martin Sauer
Prodigy 190 points

Part Number: DP83867IS

Hello,

in our design we use the DP83867ISRGZ as 1000Base-T PHY. The MDI interface is routed to a filterboard where the transformer and connector is placed. If I do the test mode 1 qualification measurement I will get a fault at Peak differential output.

Can you give me a tip where the problem is? 

Thank you for your help.

BR

Martin Sauer

ETH_1000BaseT_Filterboard_Mode-1.pdf ETH_1000BaseT_Filterboard_Mode-1-2.pdf 

  • 0
    TI__Mastermind 33435 points

    Hi Martin,

    Can you check that you've followed the steps outlined in section 3.6 of our DP83867 troubleshooting guide? Compliance testing can be sensitive to board layout so you want to be sure there are minimal vias, and that differential pair matching is good on the MDI lines.

    Furthermore, are you using the test scripts detailed in our DP8386x compliance app note?

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Prodigy 190 points

    Hi Shane,

    in the troubleshooting guide, I can find the following 

    Where can I find the register description of the PHY?

    BR

    Martin

  • 0 in reply to Martin Sauer
    TI__Mastermind 33435 points

    Hi Martin,

    Register descriptions are located in section 7.6 of the datasheet.

    Is your layout following the layout recommendations in the linked troubleshooting guide? Its best to optimize the layout first when compliance testing as these tests are sensitive to layout. I'll attach our layout checklist here as well: 7024.SNLR048A.xlsx

    Furthermore, are there any functional issues with the ethernet interface or is this purely a compliance concern?

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Prodigy 190 points

    Hi Shane,

    there aren't any other issues. Functionally, the system works without any problems.

    Layout isn't perfect, because the transformer and connector are on the customers filterboard, both PCB are connected with a short flat cable. From the PHY to the flat cable connector the traces have a 0402 resistor and are time-aligned. The resistors are present due to the circuit.

    BR

    Martin

  • +1 in reply to Martin Sauer
    TI__Mastermind 33435 points

    Hi Martin,

    Thanks for the details. It may be that the layout is contributing to this but its good that you do not see functional issues.

    Out of curiosity, what circuit necessitates the 0402 resistors between the PHY and the flat cable? MDI lines typically route straight to the transformer similar to the below image on our DP83867-S-EVM.

    • The reason I ask is that 0402 resistor pads are wider than the MDI trace and may cause slight impedance discontinuities. This combined with the use of a flat cable could impact performance on sensitive compliance tests.

    One thing to check as well: Does the transformer meet the specs in the DP83867 datasheet? Magnetics with the incorrect specs can impact the MDI signal as well.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Prodigy 190 points

    Hi Shane,

    we need the resistor because on pair A and B there is a selection between 1000Base-T PHY and 1000Base-T1 PHY.

    D1700 is DP83867IS. On the filterboard of our customer is a WE 749020023A transformer.

    BR

    Martin

  • 0 in reply to Martin Sauer
    TI__Mastermind 33435 points

    Hi Martin,

    Co-lay options on the MDI lines are not recommended due to the sensitivity of these signals. That being said, you're passing all compliance tests on pairs A and B so this may be ok. The 749020023A transformer you're using has a turns ratio tolerance of 5%, which is out of the spec for recommended magnetics. The DP83867 datasheet specs 2% as the maximum tolerance on transformer turns ratio.

    The layout on pairs C and D could be improved by:

    • Removing the resistors on these pairs (seems like they are unnecessary)
    • Routing the traces on one layer to avoid vias. Vias add bends to the signal path that are not ideal for high speed signals as they can cause reflections.
    • Make sure there is a solid GND plane under traces. You may already have this but I cannot tell from the image
    • Mounting the magnetics and RJ-45 on the same PCB as the PHY. I would expect this to have the largest impact as a flat cable would introduce loss and impedance discontinuities from the cable itself and the connectors on either side. 
    • Swap magnetics to have a better turns ratio tolerance.

    Compliance testing is a higher bar to meet than functional communication so having a optimal layout is important. I'd suggest improving this if possible before tuning the A0-A3 registers.

    Is passing compliance a requirement, or is functionality sufficient? We've seen cases in the past where marginal failures on compliance do not impact functionality so it would help to know the end goal.

    Best,

    Shane