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Original question:

DP83TC817S-Q1: CLKOUT for MCU clocking?

DP83TC817S-Q1: PTP_PLL - how to set up?

Henrik Glader
Prodigy 10 points

Part Number: DP83TC817S-Q1

I've tried to clock the "PTP Reference Clock" as stated in <SNLS779A – JULY 2025 – REVISED NOVEMBER 2025>.

To change PTP_PLL to 125MHz: Writing 0x6666 to ref D35h and D36h - OK after both writes performad.

Set clock reference to PTP_PLL with 8ns step: Writing 0x1088 to ref D27h - OK.

Staring the clock: Writing 0x0004 to ref D00h - OK.

Reading clock value every second: as per page 36 7.3.1.1.2.1 "Read a time value"

Now, the clock increases twice like the increment happens on a 250MHz basis.

AM I missing something?

On a side note: I would like to bring this clock uot to the controler, Is that possible?

  • 0
    TI__Mastermind 42148 points

    Hi Henrik,

    Can you share a little more background for your use case and application of the PTP_CLK?  Is your sole use case for PTP_PLL to use the PHY for 125 MHz clock source?  Do you require PTP synchronized clock?  Also, what MII are you using?  I'm wondering if 250/125 MHz PLL clocks may also be suitable for your use case.

    I would recommend you request access to DP83TC818 secure resource folder.  In here is an AVB application note.  While the AVB part is not applicable to DP83TC817, the PTP configuration is still applicable and will help you with this.  Please see "Table 2-2. Configuration for using PTP_PLL".

    Yes, clock output signal can be brought out to GPIO pin.  See section "PTP Clock Output" in DP83TC817 data sheet.  The AVB application note contains details on "CLKOUT_MUX_CTL" register.  Note integer divider range of 2-255.

    Thanks,

    Drew

  • 0
    Prodigy 10 points

    Hi Drew, and thank you for your response : )

    I am aiming to use a tick, related to the PTP precision time clock, to minimize the burden of synchronizing the micro controller reference timer.

    I assumes that PTP_PLL (at the follower) can be tuned to the recovered clock instead of setting a sub-nano value in the PTP_RATE registers.

    Then by sending this PTP_PLL to the main micro controller, it's tick rate would match leaving only the absolute time to be established.

    The XI versus recovered clock ratio works and matches precision frequency counter very well.

    What is left is to verify the PTP time at PTP_PLL tick rate, where I used 125M to get a ball park verification, which failed.

    The next step is to send this tick out to the MCU, probably around 250M divided by PTP_COC at 2, hence 125M but following the recovered clock.

    We are using RMII at this time due to MCU supporting that or MII, but that is not a requirement.

    The AVB app. may spread some light on mysterious registers including DA8h = ).

    /Henrik

  • 0 in reply to Henrik Glader
    TI__Mastermind 42148 points

    Hi Henrik,

    Thanks for the background, sounds like an interesting application.  Let us know if you have any trouble with the AVB application note.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hi Drew : )

    Indeed, got some progress.

    Another undocumented register was introduced (D97h) and now the PTP time increases accordingly.

    On that note, the SNLS768A (page 30) states "802.1AS Synchronised Clock Frequency 50MHz maximum".

    I will therefore need to keep tick rate 20ns or lower me asumes, well I'll soon knows...

  • 0 in reply to Henrik Glader
    Prodigy 10 points

    And finally, with some more tests, all boxes are checked = )

    There were more bits to set....

    On the 50MHz spec, I've pushed it to 75MHz with maximum drive strength so I'll stick with 50MHz.

    Noticed that the PLL would easily go beyond 300MHz but, of course, that was only for fun.

    Thank you Drew.

  • 0 in reply to Henrik Glader
    Prodigy 10 points

    One for the road...

    If PTP_PLL is set to 250MHz the PTP_COC divisor does not do the trick and gives a different output clock frequency than expected.

    With PTP_PLL id does how ever work.

    There is probably something somewhere that explains this effect...