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Original question:

SN65DSI86: The DP display can't output normally

SN65DSI86: DP output sometimes not shown

zhou liang
Prodigy 20 points

Part Number: SN65DSI86

Hi TI experts

We are testing MIPI to DP. During testing, we found that the DP display sometimes does not display. The register information is as follows.

```
root@valuemon64 sunhv1:/var/lib/systemd/coredump# i2cdump -f -y 4 0x2c
No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 36 38 49 53 44 20 20 20 02 00 84 00 00 01 00 00    68ISD   ?.?..?..
10: 26 00 58 00 00 00 00 00 00 00 00 00 00 00 00 00    &.X.............
20: 80 07 00 00 38 04 00 00 00 00 00 00 60 00 00 00    ??..8?......`...
30: 10 00 00 00 60 00 0c 00 80 00 20 00 00 00 00 00    ?...`.?.?. .....
40: 2c 46 00 00 80 00 c0 08 74 04 c0 00 1c 00 60 00    ,F..?.??t??.?.`.
50: 10 00 80 07 38 04 00 00 40 e4 0d 01 10 00 f0 00    ?.??8?..@????.?.
60: a0 60 a4 00 20 06 00 00 00 00 00 00 00 00 00 00    ?`?. ?..........
70: 00 00 00 00 00 01 02 01 80 01 00 00 00 00 00 00    .....?????......
80: 00 00 00 00 00 00 00 00 00 1f 7c f0 c1 07 1f 7c    .........?|????|
90: f0 c1 07 24 82 10 01 04 01 00 00 00 00 00 00 00    ???$?????.......
a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............
b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c    ?x???l???\\\????
c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00    ???.............
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 01 00 00 00 00 00 06 00 00 00 00 00 00 00 00 00    ?.....?.........
f0: 00 00 00 00 00 00 40 01 00 00 00 00 00 00 00 00    ......@?........
```

What could be the possible cause? 

Thanks

Best regards

Zhou Liang

  • 0
    TI__Mastermind 24835 points

    Hi Zhou,

    Allow me some time to process the log and determine any debug path, please give me 1 business day to analyze.

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    TI__Mastermind 24835 points

    Hi Zhou,

    My initial analysis of the logs report that the CSR registers indicate DP Data underrun error, which is triggered when no data is received when Data should be ready (0xF6 = 0x40). Additionally, the other register indicates loss of DP Sync Lock error (0xF7 = 0x01) - happens whenever DP sync generator has lost lock with the DSI sync stream.

    Do you have more specific details about the system? The rest of the registers indicate no issues at the DSI input, could this be a sequencing issue?

    Please let me know any sequencing details, configuration details regarding the system setup, and other information if you have additional questions for the debug.

    Thank you for your patience,

    Miguel

  • 0 in reply to Miguel Bolante
    Prodigy 20 points

    Hi Miguel

    Thank you for your analysis. We are using IMX8MP with the mainline/community Linux driver. After investigation so far, it appears there might be a timing issue in the driver when handling hot-plug events. I am still looking into it.

    BTW, Can you provide an example driver build in linux for this chip?



    Zhou Liang

  • 0 in reply to zhou liang
    TI__Mastermind 24835 points

    Hi Zhou,

    zhou liang said:
    there might be a timing issue in the driver when handling hot-plug events. I am still looking into it.

    Thank you for the context!

    zhou liang said:

    BTW, Can you provide an example driver build in linux for this chip?

    (+) [FAQ] SN65DSI8x Programming Tools - Interface forum - Interface - TI E2E support forums

    Please refer to this guidance regarding programming with the SN65DSI86, I believe there is an example directory that shows a DSI -> LVDS bridge source code, this may be what you are looking for.

    Please let me know if there are any additional questions!

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    Prodigy 20 points

    Hi Miguel,

    I made some modifications to the driver, and now the UNDER RUN issue no longer occurs during DP plug/unplug events.

    Original configuration steps:

    1. Reset DSI host, config DSI host, make sure DSI clock and data lane state are in stop state
    2. Config DSI host display timing and enable DSI video
    3. Config ti-sn65dsi86 DSI_A lane config, DSI CLK frequency, DP lane config
    4. Execute ti-sn65dsi86 link training
    5. Config video parameters
    6. Enable video stream by setting VSTREAM_ENABLE to 1

    Modified configuration steps:

    1. Reset DSI host, config DSI host, make sure DSI clock and data lane state are in stop state
    2. Config ti-sn65dsi86 DSI_A lane config, DSI CLK frequency, DP lane config
    3. Execute ti-sn65dsi86 link training
    4. Config video parameters
    5. Config DSI host display timing and enable DSI video
    6. Enable video stream by setting VSTREAM_ENABLE to 1

    In other words, I moved Step 2 (DSI host display timing config and DSI video enable) from the original sequence to right before Step 6 (VSTREAM_ENABLE) in the modified sequence.

    According to the chip datasheet Section 8.4.2 Power-Up Sequence, the last two steps are:

    1. Video stream can be enabled in the GPU and sent via the DSI interface to the SN65DSI86.
    2. SW can now enable the SN65DSI86 to pass the video stream provided on the DSI interface to the DisplayPort interface by writing a 1 to the VSTREAM_ENABLE register.

    This indicates that the DSI host video output should be enabled after configuring the SN65DSI86 and completing link training.

    Previously, the UNDER RUN issue occurred during hot-plug. During the hot-plug process, I monitor the HPD events in register 0xF5. When the DP is unplugged, the ENABLE pin of ti-sn65dsi86 is not pulled low. However, the datasheet only provides the Power-Up Sequence, but there is no configuration timing sequence documented for hot-plug scenarios.

    My Question: Is my modification (moving the DSI host configuration before VSTREAM_ENABLE) appropriate for the hot-plug scenario? Is there any potential risk with this change?

    Any insights or confirmation would be greatly appreciated!

    Thank you!

    Best regards

    Zhou Liang

  • 0 in reply to zhou liang
    TI__Mastermind 24835 points

    Hi Zhou,

    Let me provide some feedback on the original change from the issue seen before - it sounds like the device was not configured to receive DSI side information before the input was sent to the device, so mismatch in received and expected (maybe default) timings could be causing this issue.

    For hot-plug scenario, in other products this is considered to be a new instance of the power sequence, so I recommend re-initializing the with same steps again before enabling the VSTREAM_ENABLE to ensure all interruptions are cleared from the hot plug event.

    zhou liang said:
    My Question: Is my modification (moving the DSI host configuration before VSTREAM_ENABLE) appropriate for the hot-plug scenario? Is there any potential risk with this change?

    Since this is working properly to resolve UNDER RUN issue, I believe there's no risk enabling the host after to ensure there is alignment between expected timings and received timings from the SN65DSI86.

    My only concern is that during the times the host is not driving the DSI link, please ensure no noise or random signal can propagate at the input which could be misinterpreted or cause corruption at the TX of the device.

    Thank you for your update and double checking the hot-plug restoration mechanism.

    Best,

    Miguel