Hello Nukunj,

Thanks for your query.

Nikunj Zadeshwariya said:

1) does it support detection and booting up directly on x8 OSPI.

A1. I have an access to the MT35XU02GCBA2G12 brief data sheet only from which I see this NOR flash memory is able to be booted from in the 8x DDR mode.

The AM62A7 ROM boot requirements to flash memories are specified in the Chapter Initialization / Section, xSPI Boot and its Subsection, xSPI Bootloader Operation of the AM62Ax TRM 

From AM62A7 ROM point of view, it looks like this memory can not be booted from in OSPI boot mode (SDR: 1S-1S-8S ) but only in the AM62A7 ROM  xSPI (extended SPI) DDR boot mode: 8D-8D-8D. I need to know whether the MT35XU02GCBA2G12 memory supports the 8D-8D-8D format in xSPI mode, the type of supported xSPI read commands, etc. to confirm whether it is compliant with the SoC ROM loader. 

Indeed the brief MT35XU02GCBA2G12 datasheet specifies:

While 8-bit size support confirmed for xSPI address and data, I am still not sure whether the supported command size in xSPI mode is 8-bit (8D-8D-8D).

Would you please share per the E2E private chat the full documentation if available on your side.

Nikunj Zadeshwariya said:

SK-AM62P-LP uses W35N01JWTBAG, is the detection and booting up starting from powered on works on x1 or x8 SPI?

A2. The original SK-AM62P-LP (\sprr487c\Proc164\2_PROC164E2\1_SCHEMATIC\PDF) uses the NOR Flash S28HS512TGABHM010. According to design note It can be replaced with the footprint-compatible W35N01JWTBAG octal serial NAND Flash memory. From the brief datasheet it looks like, the octal serial NAND Flash W35N01JWTBAG is able to boot in standard x1 and x8 boot modes.

From AM62A7 ROM point of view, I suspect  that:

the AM62A7-Q1 ROM serial NAND boot 1s-1s-1s or 1s-1s-8s may not be supported, because of misalignment in address-size for the memory 4-KB page read command between the ROM and the W35N01JWTBAG. I need to crosscheck this internally. I hope I can get back to you in 2 or 3 days.

Thanks for your patience !

Best Regards

Anastas Yordanov

Hello Anastas,

Thank you for detailed response. I found that in micron datasheet MT35XU02GCBA2G12, it is mentioned that it supports Extended-SPI protocol with octal commands.

1) Will MT35XU02GCBA2G12 work with AM62A74?

2) What are the changes needed from our end using TI-SDK. For which the separate thread from my teammate is ongoing:

AM62A7: Not able to detect NOR Flash x8 OSPI in SDR Mode - Processors forum - Processors - TI E2E support forums 

Thanks,

Nikunj

Hello Nikunj,

Thank you for the update. I will consider it.

Would you please specify your SDK type and version.

So I can refer your software query to the appropriate SDK team.

Thanks

Best Regards

Anastas Yordanov

Hello Anastas,

TI SDK Version:
ti-processor-sdk-linux-edgeai-am62a-evm-10_01_00_05

You may refer another ongoing thread  AM62A7: Not able to detect NOR Flash x8 OSPI in SDR Mode for more details. It would be helpful if our teams get aligned to this and bring the resolution at the earliest.

Thanks,

Nikunj

Also, from the Hardware perspective,

can you please confirm whether MT35XU02GCBA2G12 is compatible with AM62A74 or not? will the software change (with required xSPI DDR boot mode: 8D-8D-8D) on SDK resolve this issue?

This would help us plan our design change at earliest if at all required.

Thanks,

Nikunj

Hello Nikunj,

I would like to apologize if my misunderstanding came from the picture:

I had a discussion, in which it became clear to me that the "I/O Pin Configuration Option" selection values: 1 and 2  might have a semantic ( bus width + data rate for data transfer upon memory reset ) which is different than what I initially understood (1: lack of support for DDR mode, 2: lack of support for SDR mode ).

The brief document version does not have the complete descriptions. From your linked thread I understand that the MT35XU02GCBA2G12 supports x8 OSPI SDR which is good.

There are some other questions myside:

Nikunj Zadeshwariya said:

1) does it support detection and booting up directly on x8 OSPI.

Q2) Do you ask about AM62A7, AM62P ROM booting or also your custom Linux bootloaders booting ? 

The AM62A7, AM62P ROM loaders have transfer speed / configuration constraints. For custom bootloaders choice is more relaxed.

The boot images loading from the flash memory over OSPI to the OCMRAM or an external LPDDRx RAM memory and bootloader execution from the RAM memory has been mostly tested and recommended. 

Nikunj Zadeshwariya said:

Also, from the Hardware perspective,

can you please confirm whether MT35XU02GCBA2G12 is compatible with AM62A74 or not? will the software change (with required xSPI DDR boot mode: 8D-8D-8D) on SDK resolve this issue?

Nikunj Zadeshwariya said:

Will MT35XU02GCBA2G12 work with AM62A74?

As I said earlier in the post I now have understanding that the default (memory reset) transfer mode / bit width of the MT35XU02GCBA2G12 might be x8 Octal DDR. If this is the case the AM62A7 ROM will not be able to boot from it in OSPI boot mode (1s-1s-8s). I need to crosscheck and confirm this as this might explain the error messages observed in the linked thread. In addition from the brief datasheet I can not understand if the memory default Bit width DDR format is 8D-8D-8D or no. 

The AM62A7 ROM can boot from the MT35XU02GCBA2G12 NOR flash memory in xSPI Boot Mode, provided that 8D-8D-8D format is supported by it, and memory's 8D-8D-8D communication protocol satisfies the following AM62A7-Q1 ROM requirement:

i.e. memory shall interpret correctly the Read commands: 0x0B or 0xEE followed by a 4-Byte address.

Nikunj Zadeshwariya said:

2) SK-AM62P-LP uses W35N01JWTBAG, is the detection and booting up starting from powered on works on x1 or x8 SPI?

The AM62P ROM booting from a serial Octal DDR NAND memory like W35N01JWTBAG shall be supported in Serial NAND Boot mode. As I refer to the AM62Px TRM, Chapter, Initialization / Section, Boot With OSPI Controller / Section, Serial NAND Boot :

and based on the fact that: "SK-AM62P-LP uses the W35N01JWTBAG NAND flash for booting" I conclude that the Octal Serial NAND flash W35N01JWTBAG is able to be booted from the AM62P ROM in both x1 SDR (1s-1s-1s) and x8 SDR (1s-1s-8s) . 

The BOOTMODE[8:7] pins will define whether x1 SDR or x8 SDR is used:

I will be able to follow-up with final confirmation from our OSPI hardware and OSPI Linux driver expert the next week.

Thanks for your patience !

Best Regards

Anastas Yordanov

Hello Nikunj,

I would like to apologize for the big time gap in my response.

Nikunj Zadeshwariya said:

TI SDK Version:
ti-processor-sdk-linux-edgeai-am62a-evm-10_01_00_05

You may refer another ongoing thread  AM62A7: Not able to detect NOR Flash x8 OSPI in SDR Mode for more details. It would be helpful if our teams get aligned to this and bring the resolution at the earliest.

Nikunj Zadeshwariya said:

Also, from the Hardware perspective,

can you please confirm whether MT35XU02GCBA2G12 is compatible with AM62A74 or not? will the software change (with required xSPI DDR boot mode: 8D-8D-8D) on SDK resolve this issue?

From my hardware considerations in the previous posts and based on the excerpt of the FAQ: (+) [FAQ] OSPI FAQ for Sitara/Jacinto devices - Processors forum - Processors - TI E2E support forums:

 I can assume that the NOR flash MT35XU02GCBA2G12 similar to the MT35XU512ABA1G12 may be to a great extent hardware compatible with the AM62A7 SoC. 

One major difference to point out is the C-option, which stands for a stacked 4-die flash memory for the MT35XU02GCBA2G12. The MT35XL512ABA1G12-0SIT is monolithic (single die). I am not sure if this adds any variations to the memory access protocol / timings in some way.

If OSPI boot mode (SDR 1S-1S-8S)  shall be supported by the AM62A7 ROM with the MT35XU02GCBA2G12, a package with a hardware reset pin is highly recommended. A hardware reset activated during warm resets/reboots will make memory switch from a 4-Byte address mode (2Gbit is typically covered with a 32-bit address) to a default 3-Byte address mode which is the only address mode supported by the ROM for NOR flashes in the OSPI boot mode. In the xSPI  SDR boot mode: 1S-1S-1S the ROM outputs a 3-Byte address, but in 8D-8D-8D the ROM outputs a 4-Byte address. 

I assume you plan to attach only one flash memory (using only one CS line) to the AM62A7 OSPI port.

Please refer also the below thread:

(+) AM2432: Inquiry regarding AM2432 OSPI Booting - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

I will let the experts from our hardware and Linux SDK software team confirm on the AM62A7 vs MT35XU02GCBA2G12 memory compatibility.

Please ping this thread if not responded by Tuesday (April-28-2026) next week.

Best Regards,

Anastas Yordanov

Looks like this is being worked on below thread and waiting on info from Micron:  AM62A7: Not able to detect NOR Flash x8 OSPI in SDR Mode 

Regards, Nuruddin

Hi Nuruddin,

Thanks for your confirmation.

BR,

Anastas Yordanov

Nikunj, Nuruddin,

It seems that the resolution of this thread depends on the resolution of these two threads:

AM62A7: Not able to detect NOR Flash x8 OSPI in SDR Mode - Processors forum - Processors - TI E2E support forums, itself dependent on:

AM62A7: Not able to detect NOR Flash x8 OSPI in SDR Mode during Kernel boot - Processors forum - Processors - TI E2E support forums

In order for last one to be resolved, we are waiting for more data to be provided by Micron !

Thanks

Best Regards

Anastas Yordanov