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DS250DF810: DS250DF810 Low-Temperature Error and TX FIR Optimization Guide

Part Number: DS250DF810
Other Parts Discussed in Thread: DS280DF810

1. System Topology & Channel Information

  • Main SoC: Broadcom QAX (100G Ethernet)

  • Retimer: TI DS250DF810

  • PCB Material: Panasonic Megtron 6 (Ultra-low loss)

  • Channel Reach:

    • Host Side: BCM → 20cm (approx. 8 inches) → DS250DF810

    • Line Side: DS250DF810 → 10cm (approx. 4 inches) → QSFP28 Connector

  • Data Rate: 25.78125 Gbps per lane (100G Base-SR4/LR4)

2. Issue Description & Observation

  • Environmental Test Failure: Bit errors were detected during low-temperature chamber testing.

  • Time-dependent Error: Using the room-temperature optimized settings, errors consistently occur after approximately 8 hours of continuous operation in low-temperature conditions.

  • TX FIR Sensitivity: We observed high sensitivity when adjusting the DS250DF810 TX FIR settings. (Main 12, Post 3, Pre -1, Main 8, post 0, Pre 0.......Widely applied.)

3. Technical Inquiries

  1. Best Practice: Given the extremely short line-side reach (10cm / <3dB insertion loss on Megtron 6), what are the recommended TX FIR (Main/Pre/Post) guidelines for the DS250DF810?

  2. Host-side reach (20cm / <7dB insertion loss on Megtron 6), what are the recommended TX FIR (Main/Pre/Post) guidelines for the DS250DF810?

How can we mitigate errors induced by low-temperature conditions in this specific configuration? 

  • Hi Lee,

    Apologies for the delay and thanks for the system information.  I have a few questions:

    1. In terms of the channel, is this bi-directional, or only system egress (i.e. BCM -> DS250DF810 -> QSFP28). 

    2. Do you start observing continuous bit errors after ~8 hours of testing in low temperature?  Or just a small burst and then zero bit errors for a while after?

    3. Is it possible to enable the PRBS checker on the DS250DF810?  We can use this to determine whether bit errors are occurring between the BCM -> DS250DF810 or DS250DF810 -> Optical Module.

    Thanks,

    Drew

  • 1. Channel Directionality

    The channel is bi-directional. Please refer to the attached block diagram for the detailed signal flow. It covers both the egress (BCM => DS250DF810 => QSFP28) and the ingress (QSFP28 => DS250DF810 => BCM) paths.

    2. Error Pattern (Low Temp)

    After ~8 hours of testing, we observe burst errors occurring at minute-level intervals, rather than a continuous stream.

    3. PRBS & Loopback Setup

    Yes, the PRBS checker can be enabled. To isolate the issue:

    • BCM Side: We will enable Loopback on the BCM chip.

    • Retimer Side: We will verify the path from Retimer #2 to Retimer #1 to check the segment between the QSFP28 and the host.

  • Hi Lee,

    Thanks for the update, looking forward to your test results.

    A few other thoughts:

    • You might compare a register dump of DS280DF810 at room temperature vs cold temperature (with errors) to see if any differences stand out.
    • What adapt mode are you using?
    • What eye opening do you observe on DS280DF810 (registers 0x27, 0x28)?  Is this impacted at cold temperature?

    Thanks,

    Drew

  • Hi Drew,

    Thank you for the follow-up. Based on your suggestions, I have checked the register values and the adaptation settings. Here are the results:

    • Adapt Mode: We are currently using Mode 2.

    • Eye Opening (Registers 0x27 & 0x28): 

       - Normal Temperature: Register 0x27 ranges from 0x10 to 0x13, and 0x28 ranges from 0x5C to 0x64.

       - Cold Temperature: Register 0x27 ranges from 0x10 to 0x12, and 0x28 ranges from 0x52 to 0x64.

    • PRBS Test 1 : Retimer #1 (PRBS EN) -> QSFP (Optic loop) -> Retimer #2 (PRBS Checker) Result: No error counts.

    • PRBS Test 2 : Retimer #2 (PRBS EN) -> BCM -> Retimer #1 (PRBS Checker) Result: Test unavailable.(BCM - Not an Ethernet frame)

  • Hi Drew,

    I have an additional question.

    Regarding registers 0x71-0x73 (DFE Taps), I noticed the values remain static even in Adapt Mode 2/3 and during Continuous DFE Adapt reg set.

    Is it expected for these registers to show no variation once the link is stable?

    Or should I be checking a different register to monitor real-time DFE changes?