Part Number: DS110DF410
Dear Team,
Despite the successful EEPROM load, we are unable to establish a link between the processors. The SGMII interface is not "pinging" across the retimer path.
Request for Information :
Register Verification:
1. Is there a specific procedure to read back the active register values from the Retimer to verify that the EEPROM data was mapped correctly to the internal registers?
Read the retimer registers using processor and control/shared registers can be accessed correctly but observed all channel registers are zeros (channel registers read using 0xFF→0x04 / 0x0C).
2. Using the SigCon Architect application, the register updates were applied and a corresponding .hex file was generated. The generated hex file was reloaded into the application using the 'Load from Hex File' option and 'Update from Slot to Device' However, when the channel registers were read back, they did not match the values that were written. Are there specific steps for verifying the generated hex file?
3. After loading the EEPROM and EEPROM →Retimer (All done_Low), the channel registers do not reflect the loaded data when read back.
Could you suggest specific methods for EEPROM data writing or read back from retimer or file generation to resolve this?
Note: The SGMII interface throughput verified in Slave Mode cannot be replicated in Master Mode. Kindly suggest a solution to make Master Mode functional.
Regards,
Veeramanikandan S