TCAN4550-Q1: Query on TCAN4550 Interrupt Handling for RX Communication

Hello Ankita,

I believe you can find what you need in the following two documents:

TCAN45xx Software User's Guide (Link)

MCAN User's Manual (Link)

The TCAN4550 uses the CAN FD Controller "MCAN" developed by Bosch.  The IP was used without modification except for the register addresses where the TCAN4550 has added an offset of 0x1000 to each register address.  For example, the Control Register is listed in the MCAN User's Manual as 0x18, but in the TCAN4550 it is 0x1018 due to the offset.  Also note that the TCAN4550 only has 2k of MRAM, but the MCAN IP can support configurations that exceed 2k, so some care must be taken to not use more than 2k of MRAM in your configuration.  Outside of the register address difference, the information in the MCAN User's Manual is directly applicable to the TCAN4550 and this document can be used as a supplement to the TCAN4550 with regards to MCAN.

You can enable/disable the MCAN interrupts in the Interrupt Enable Register 0x1054.  If you do not want to receive the RF0N interrupt, but only the RF0W, then you will need to set RF0NE = 0 and set RF0WE = 1.

The 0x0800 register addresses are not related to MCAN.  The configuration register 0x0800 and device related interrupt register 0x0820 are used for features such as the watchdog which is not MCAN related.

The MCAN Interrupt Register is 0x1050 but has a "read only" copy with address 0x0824 that is placed adjacent to the device interrupt register 0x0820.  This allows both oxo820 and 0x0824 interrupt registers to be read in a single SPI Read transaction with Length=2 preventing the need to do two separate SPI reads to registers 0x0820 and 0x1050 saving time.  However, if any MCAN interrupt bits are set they will need to be cleared with a write to register 0x1050.

MCAN has two Interrupt Lines that can be used to isolate different interrupts into different interrupt lines.  You can use the Interrupt Line Select register 0x1058 to assign the different MCAN interrupt bits to the different lines.  The GPIO1 and GPO2 pins can also be used as additional hardware interrupt lines if you have connected them to the MCU.  You can enable or disable the MCAN interrupt lines using the Interrupt Line Enable register 0x105C.

The nINT pin is a Global interrupt pin that will reflect all enabled interrupt bits in registers 0x0820 and 0x0824 (which includes MCAN).  It is OK if this is your only hardware interrupt pin used, but note that it will reflect more than MCAN interrupts.  If you only care about MCAN interrupts, then using the GPIO1 or GPO2 pins can allow you dedicate the pin for very specific interrupt bits.  However, this does not prevent them from also being reported on the global nINT pin but it does give you options to set priority levels for different interrupts if desired.

I hope this addresses your questions.

Regards,

Jonathan

Hi Jonathan,

Thank you for the reply.

Our main confusion is that when we probe the INT line, we observe an interrupt being generated for every 26 messages (as per the configured watermark level). However, at the driver level, the control is not entering the watermark-based interrupt handling condition; instead, it is consistently going into the RF0N (new message) interrupt condition.

Based on the driver flow, we would expect interrupts to be triggered for every message, but that is not what we are observing. Therefore, we would like to understand why this behavior is occurring and what the exact interrupt handling flow is.

I hope this clarifies the issue we are trying to convey.

Regards,
Ankita

Hi Ankita,

Ok, so I understand that your question is not with how to enable the registers, and the device is setting the appropriate interrupt bits as you expect.  

You may need to adjust your interrupt service handling routines to work for your application.  I support the TCAN4550-Q1 at the device level and help you with register configuration, or issues you experience with using the device.  

I'm not sure what your routines currently look like, but at a high level I would think when you see the watermark interrupt bit, you would need to clear that, and then start reading the messages out of the RX FIFO.  The process for reading a message from the RX FIFO is the same for when you set an interrupt to read it after every new message that has arrived or whether you wait for multiple messages to arrive in the RX FIFO before starting to read the messages.  You will just need to read the messages frequently enough to prevent an overflow condition that would result in data loss.

Regards,

Jonathan

Hi Jonathan,

Thank you for the reply.

As mentioned earlier, we have a 60 ms watchdog timer enabled in the TCAN driver to ensure data is read even when the RX FIFO watermark level is not reached.

In this context, we would like to understand which interrupt bit should be checked within the m_can interrupt service routine to handle this condition.

Currently, we are using IR_RF0W to detect the FIFO watermark interrupt. However, we would like to know how to handle the scenario where the watermark level is not reached and data needs to be read based on the watchdog timer trigger. Specifically, which interrupt field should be monitored in this case, and how should this flow be managed alongside the watermark-based handling?

We would appreciate your guidance on this.

Regards,

Ankita

Hello Ankita,

The TCAN4550-Q1 has three different sets or groupings of registers each with a different address range, and there is a fourth SPI address range for the MRAM.

The MCAN specific registers have an address range of 0x1000 to 0x10FC and the MCAN specific Interrupt register has an address of 0x1050.

The non-MCAN registers that relate to the other functions of the device have an address range of 0x0800 to 0x083C and the non-MCAN Device Interrupt register has an address of 0x0820.

The RX FIFO Watermark (RF0W) bit is bit 1 in register 0x1050.  

The Watchdog Time Out (WDTO) is bit 18 in register 0x0820.

Note that register 0x0824 in the non-MCAN address range is a Read-Only copy of the MCAN Interrupt register 0x1050 that has been created so that both interrupt registers could be read in a single SPI transaction with the Length field set to 2.  If the MCU is configured to do this, it would still need to clear any MCAN bits through a write to register 0x1050.

For your application, I'm assuming when you get a watchdog timeout interrupt, you would just need to run the same routine to read and clear the RX FIFO you use when getting a RX FIFO Watermark interrupt.

Regards,

Jonathan