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TUSB1310A: TUSB1310A power up flow

Kfir Tito
Prodigy 10 points

Part Number: TUSB1310A
Other Parts Discussed in Thread: TPS65000

Dear Team,

I'm using TUSB1310A as a USB3 PHY device connected to a host (PC) and driven by a link layer - Synopsys controller IP over an FPGA device.

Currently, I do see my XTAL 40MHz but I don't see PCLK toggling after RESETN is released.

OUT_ENABLE is connected to pin PG_N at TPS65000 (step-down converter that generates 1.8V and 1.1V from 3.3V input) according to the reference design: 6724.superphy_usb_b_ulpi_1205.pdf

Board straps configurations: (using 4.7K PU/PD resistors) - also measured with a scope:

PIPE_16BIT (PHY_STATUS) = 0 (PIPE MODE ON)
XTAL_DIS (RX_ELECIDLE) = 0 (XTAL)
REFCLKSEL1:0 (ULPI_DATA5:4) = 11 (40MHz)
ULPI_8BIT (ULPI_DATA6) = 0 (ULPI MODE OFF)
ISO_START (ULPI_DATA7) = 0 (PIPE ISOLATE MODE OFF)
SSC_DIS (TX_MARGIN0) = 0

Need your support with a few questions:

1. For USB3 (PIPE) - is the ULPI connection also required? Is it mandatory for chip power-on? (Is ULPI reset necessary for PIPE to be ready?) Must the link layer contain a ULPI I/F?
2. Is OUT_ENABLE implemented correctly? Is it okay that OUT_ENABLE will rise with 1.8V (VLDO1)?

  • 0 in reply to Kfir Tito
    TI__Guru**** 161276 points

    Hi Kfir:

      TUSB1310A is NRND and could be end of life in any time.

    Regadrs

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 10 points

    Hello Brian,

    I realize that TUSB1310A is NRDN, but since it's still being offered for sale and we have a quantity of boards that we need to use
    for pre si emulation , we asking to get your support.

    Thanks a lot.

    ***update - once I increased the 1V1 to ~2V I do see the PCLK toggling.
    asking again - ULPI is mandatory even if I working in PHY_MODE = USB3 and PHY_STATUS = PIPE ? if so why ? for the power up sequence / software reset ?

  • 0 in reply to Kfir Tito
    TI__Guru**** 161276 points

    1.2v or 2v?2v is too high, should be <1.3v.

    I will review schematic first.

    Best

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 10 points

    Hi ,

    yes but it was just for out_enable debug . i fixed the issue (eco)
    I do see the PCLK. on 1V1

    During the POWER UP SEQ = 

    I saw in 5.3.1.2 ULPI Reset: Software Reset
    Is this flow is necessary in case of USB3 MODE only ?
    Is ulpi interface muxt be connected to TUSB ?

    Thanks again.

  • 0 in reply to Kfir Tito
    TI__Guru**** 161276 points
    Kfir Tito said:
    I saw in 5.3.1.2 ULPI Reset: Software Reset
    Is this flow is necessary in case of USB3 MODE only ?
    Is ulpi interface muxt be connected to TUSB ?

    From ULPI spec, a Software Reset is needed as well after power up.

    for TUSB1310A, DIR will go low after TUSB1310A coming out of power on reset and ULPI data is 04, so it's not required to do another software reset .

    Best

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 10 points

    Hi Brian,

    Thank you for the clarification.

    I can confirm that in our setup, DIR successfully goes low and the ULPI data lines output 04h as expected following the hardware power-on reset.

    Regarding Dual-Role / OTG operation, I have a follow-up question regarding how the role (Host vs. Device) is determined and negotiated:

    Which layer or mechanism is responsible for explicitly configuring the TUSB1310A into Host or Device mode?

    According to our interpretation of the ULPI specifications, when configured or acting as a Device, we expect bit 6 (IdGnd) of the RX CMD byte to be set to 1 (indicating the ID pin is floating/high-impedance). Could you confirm if the TUSB1310A automatically updates this bit based on physical ID pin sampling, or if the Link controller must explicitly drive the role change via ULPI register overrides?

    Best regards,

    Kfir Tito

  • 0 in reply to Kfir Tito
    TI__Guru**** 161276 points

    Hi Kfir:

       TUSB1310A does not support OTG function since there is no ID pin .

    Best

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 10 points

    Thanks,


    Another Q, regarding jtag signals.
    according to the datasheet, table 3-6 required external PD on JTAG_TRSTN (we don't have),
    this can be an issue ? or only required for JTAG functionality ?

    BR, 

    Kfir Tito

  • 0 in reply to Kfir Tito
    TI__Guru**** 161276 points

    Hi Kfir:

      There is pulldown inside of JTAG_TRSTN pin, so it should not be an issue if no external PD.

    Best

    Brian