TCAN4550: TSD protection in low temperature

Hello Hanbing,

Hanbing Xiao said:

Has you even meet such condition that the number of CAN error frames increasing as ambient temp rising?

Yes, we have seen communication errors at higher temperatures in applications where the crystal oscillator circuit is not optimized.  Higher temperature tends to decrease the amount of parasitic capacitance that is part of the capacitive load on the crystal which can cause the amplitude of the oscillation to increase.  If the peak to peak amplitude becomes too large, the lowest level of the waveform can cause the device to think the OSC2 pin has become "grounded" which is the method used to switch the device into single-ended clock mode.  If this mode switch occurs, then there can be a momentary disruption of the clock to the digital core and MCAN controller that can result in CAN and SPI message errors if those messages coincide with a clock disruption.

Please see the TCAN455x Clock Optimization and Design Guidelines Application Report (Link) for more information on how to optimize the clock circuit.  I noticed in the schematic that there is not a series dampening resistor located between the OSC1 pin and the crystal, and that there are two different capacitance values used on the two sides of the crystal (10pF on OSC1, and 18pF on OSC2).  It also appears the 10pF cap on OSC1 is not installed.  An asymmetric capacitive loading with more capacitance on OSC2 than on OSC1 has been tested and can be stable, so this is not necessarily a problem

Hanbing Xiao said:

Is there any problem with the schematic? SCHEMATIC1 3-CAN.pdf 

A series resistor is recommended between the OSC1 pin and the crystal, to help with optimizing the circuit for stable operation across full temperature range.  Adjustments to the capacitors can be adjusted to accomplish this as well.  It is not possible to determine the correct values needed just by reviewing a schematic.

The clock circuit stability is the only known reason for higher temperature related communication errors, and I would suggest trying to optimize this circuit and try the tests with different values of capacitors to see if there is a change to the errors detected.

Hanbing Xiao said:

Why would TSD happen in 50C ambient temp. Even consider the max Isup with 12V power supply. It is not reasonable to reach 150C junction temp by calculating the thermal resistance.

TSD at 50C is not expected or common unless there is some sort of fault condition that results in large power dissipation.  How are you determining that there is a TSD event?  Can you provide any data or test results to show this?

Regards,

Jonathan

Hi Jonathan

Could you please tell me on which EE or customer project happened such problem?

Jonathan Nerger said:

we have seen communication errors at higher temperatures in applications where the crystal oscillator circuit is not optimized. 

Br

Hanbing

Hi Hanbing,

No, the issue is not related to a specific EE or customer project, and it would not be appropriate to disclose that type of information on a public forum.

The issue is due to a change in the parasitic capacitance as a result of higher temperature that lowers the total load capacitance in the crystal circuit.

If the circuit has not been optimized to have enough margin to accommodate the change in capacitance and still be within the min/max adjustment range of the Automatic Gain Control circuit in the TCAN4550's clock circuit, then the device will not be able to reduce the current flowing through the crystal when the oscillation peak-to-peak amplitude becomes too large.  If the voltage on the OSC2 pin falls below 150mV, there is a risk of the device switching to single-ended clock mode which will disrupt the digital core and MCAN controllers resulting possible communication failures on the SPI and CAN buses.

All EE's and customer projects need to optimize their designs and test across all conditions to ensure stable operation.  

Regards,

Jonathan

Hi Jonathan

Customer changed the capacitor like below, can you please help evaluate whether this configuration has problem?

Br

Hanbing

Hi Hanbing,

Yes, this configuration has been tested, simulated, and used in other applications without issues.  Each application is slightly different due to differences in the PCB layout, parasitic properties, and tolerance of the components, so it should always be tested, but there are no known problems with this configuration.

Regards,

Jonathan

Hi Jonathan

You are right. The OSC2 voltage dropped to 150mV when communication failure. But I still have below questions:

1. Is there a way to keep the clock source mode from switching, i.e., when the OSC2 voltage drops below 150 mV, to avoid using single‑ended mode?
2. When the clock source mode changing. Is it possible to have the CAN communication working normal by setting register or any other ways?
3. The CAN device’s design manual specifies that the internal recognition range for the OSC2 level is 90 – 150 mV. What is the principle behind the 90 mV lower‑limit setting?
4. If the clock source becomes disturbed, how will that affect the CAN signal waveform?
5. What are the capacitor values for the two crystal clock sources (OSC1 and OSC2) inside the device?
6. Can you provide the temperature‑drift data or curves (capacitance versus temperature mapping) for the OSC1 and OSC2 crystal capacitors?

Hanbing

Hi Hanbing,

Hanbing Xiao said:

1. Is there a way to keep the clock source mode from switching, i.e., when the OSC2 voltage drops below 150 mV, to avoid using single‑ended mode?

There is not a way to latch the clock mode.  The only way to prevent a clock mode switch is to keep the OSC2 voltage above 150mV at all times and this is done by adjusting the load capacitors and series resistor values in the circuit.

Hanbing Xiao said:

2. When the clock source mode changing. Is it possible to have the CAN communication working normal by setting register or any other ways?

No.  The clock source is used directly by the digital core and the MCAN CAN FD Controller.  Without a valid clock, the device is effectively paused until the clock is returned.  

Hanbing Xiao said:

3. The CAN device’s design manual specifies that the internal recognition range for the OSC2 level is 90 – 150 mV. What is the principle behind the 90 mV lower‑limit setting?

The device uses a voltage comparator and a weak 1uA current source on the OSC2 pin to determine whether the OSC2 pin has been connected to GND which is the configuration to use the single-ended clock mode. The comparator has a reference voltage threshold of 100mV (typical) but could vary between 90mV and 150mV due to Process, Voltage, and Temperature (PVT) conditions.

Hanbing Xiao said:

4. If the clock source becomes disturbed, how will that affect the CAN signal waveform?

Without a clock, the MCAN CAN FD Controller will be paused causing the CAN signal to be paused in whatever state it is currently in at the time of the disruption.  This could be dominant, or recessive of it was actively transmitting a message.

Hanbing Xiao said:

5. What are the capacitor values for the two crystal clock sources (OSC1 and OSC2) inside the device?

There are no physical capacitors, just parasitic pin capacitance which is approximately 9-10pF per pin as mentioned on page 6 of the TCAN455x Clock Optimization and Design Guidelines Application Report (Link).

Hanbing Xiao said:

6. Can you provide the temperature‑drift data or curves (capacitance versus temperature mapping) for the OSC1 and OSC2 crystal capacitors?

The ceramic capacitors chosen for the application will have a temperature coefficient that should define the capacitance vs. temperature profile.  

The parasitic capacitance from sources such as the PCB traces, board stackup, etc. is not something I can provide any form of temperature curve data and this will vary by application.

Regards,

Jonathan

Hi Jonathan

Thanks for answering.

Customer chose the 18nF and 0nF, and they just sent the configuration table. Can you tell the frequency is acceptable or not?

Br

Hanbing

Hello Hanbing,

The tolerance range of the oscillator frequency is defined in the CAN FD Standard and is based on the bit timing configuration.  Faster bit rates require a tighter tolerance than slower bit rates because there is a fewer number of time quantum allocated per bit.

The TCAN4550 datasheet specifies a min/max rage of +/-0.5% which would be 39.8MHz to 40.2MHz.  This tolerance is usually ok for most applications and the customer's frequency range is within this tolerance window.

Regards,

Jonathan