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TCAN4550: TSD protection in low temperature

Hanbing Xiao
Intellectual 1310 points

Part Number: TCAN4550

Hi team

Customer find that when their product is tested in high temperature. The CAN error frame number is increasing. And some chip even has TSD when the ambient temperature is 50C. Since there is little power comsumption of the chip. Can you please check the schematic below? Also give some opinion on trouble shooting direction?

  1. Has you even meet such condition that the number of CAN error frames increasing as ambient temp rising?
  2. Is there any problem with the schematic? SCHEMATIC1 3-CAN.pdf 
  3. Why would TSD happen in 50C ambient temp. Even consider the max Isup with 12V power supply. It is not reasonable to reach 150C junction temp by calculating the thermal resistance.

Br

Hanbing

  • 0
    TI__Mastermind 36551 points

    Hello Hanbing,

    Hanbing Xiao said:
    Has you even meet such condition that the number of CAN error frames increasing as ambient temp rising?

    Yes, we have seen communication errors at higher temperatures in applications where the crystal oscillator circuit is not optimized.  Higher temperature tends to decrease the amount of parasitic capacitance that is part of the capacitive load on the crystal which can cause the amplitude of the oscillation to increase.  If the peak to peak amplitude becomes too large, the lowest level of the waveform can cause the device to think the OSC2 pin has become "grounded" which is the method used to switch the device into single-ended clock mode.  If this mode switch occurs, then there can be a momentary disruption of the clock to the digital core and MCAN controller that can result in CAN and SPI message errors if those messages coincide with a clock disruption.

    Please see the TCAN455x Clock Optimization and Design Guidelines Application Report (Link) for more information on how to optimize the clock circuit.  I noticed in the schematic that there is not a series dampening resistor located between the OSC1 pin and the crystal, and that there are two different capacitance values used on the two sides of the crystal (10pF on OSC1, and 18pF on OSC2).  It also appears the 10pF cap on OSC1 is not installed.  An asymmetric capacitive loading with more capacitance on OSC2 than on OSC1 has been tested and can be stable, so this is not necessarily a problem

    Hanbing Xiao said:
    Is there any problem with the schematic? SCHEMATIC1 3-CAN.pdf 

    A series resistor is recommended between the OSC1 pin and the crystal, to help with optimizing the circuit for stable operation across full temperature range.  Adjustments to the capacitors can be adjusted to accomplish this as well.  It is not possible to determine the correct values needed just by reviewing a schematic.

    The clock circuit stability is the only known reason for higher temperature related communication errors, and I would suggest trying to optimize this circuit and try the tests with different values of capacitors to see if there is a change to the errors detected.

    Hanbing Xiao said:
    Why would TSD happen in 50C ambient temp. Even consider the max Isup with 12V power supply. It is not reasonable to reach 150C junction temp by calculating the thermal resistance.

    TSD at 50C is not expected or common unless there is some sort of fault condition that results in large power dissipation.  How are you determining that there is a TSD event?  Can you provide any data or test results to show this?

    Regards,

    Jonathan