DP83869HM: Request for Schematic Pre-Check and Ethernet PHY Design Validation – AM2634 + DP83869

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869, AM2634

Hello TI Team,

I have designed a custom industrial board based on the AM2634COLFHAZCZR (Sitara™ Real-Time MCU) along with the DP83869 Gigabit Ethernet PHY.

Before proceeding with Ethernet bring-up, PHY initialization, and continuous ping stability testing, I would like to request a detailed schematic pre-check and design validation from the TI team to ensure the hardware implementation follows TI recommended guidelines and reference designs.

Our intention is to validate the schematic thoroughly before PCB fabrication/board bring-up to avoid any Ethernet stability.

Processor : AM2634COLFHAZCZR (Sitara™ Real-Time MCU)

Ethernet PHY:  DP83869 Gigabit Ethernet PHY

Ethernet Interface:  RGMII interface between AM2634 and DP83869

Target Validation:

• Ethernet PHY bring-up
• MDIO communication verification
• PHY link detection
• Continuous ping stability testing
• Long-duration Ethernet communication validation
  

  Please review the RGMII interface between AM2634 and DP83869.

  Signals include:

  • TXD[3:0]
  • RXD[3:0]
  • TX_CTL / RX_CTL
  • TX_CLK / RX_CLK
  • MDC / MDIO

  Please verify:

  • Signal connectivity correctness
  • IO voltage compatibility
  • Pull-up/pull-down requirements
  • Trace matching recommendations
  • RGMII timing/skew implementation

  Specific Questions:

  • Should DP83869 be configured with internal delay mode or external PCB delay?
  • Are series termination resistors recommended on RGMII signals?
  • Are there any layout-critical timing considerations?
    
    3. Clock Network Verification

    ---

    Please review:

    • 25MHz crystal circuit connected to DP83869
    • Crystal load capacitor values
    • Clock routing recommendations
    • Oscillator stability requirements

    Questions:

    • Is the crystal implementation correct as per TI recommendations?
    • Are the load capacitor values appropriate?
      
      4. PHY Strap Pin Configuration

      ---

      Please verify:

      • PHY address strap configuration
      • RGMII mode strap settings
      • Bootstrap resistor values
      • Auto-negotiation configuration
      • LED strap functionality

      Questions:

      • Is the PHY correctly configured for RGMII operation?
      • Is Auto-negotiation enabled correctly by default?
      • Any strap timing or resistor concerns?
        
        5. Reset Circuit Verification

        ---

        Please review:

        • Reset topology for AM2634 and DP83869
        • Reset timing implementation
        • Reset dependency between MCU and PHY
        • Power-on reset behavior

        Questions:

        • Is the reset timing correct?
        • Is the reset sequence proper for reliable PHY initialization?
          

          Request

          Kindly review the attached schematic and provide feedback on whether the design is ready for PCB fabrication and hardware bring-up.

          Please let us know if:

          • Any schematic corrections are required
          • Any layout recommendations should be followed
          • Any Ethernet timing or PHY configuration changes are needed before fabrication
            CUSTOM_BRD_REV03.pdf