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DS25BR150: LVDS15 Standard Conforming LVDS Conforming Buffer/Repeater IC

Christian Devenish
Prodigy 10 points

Part Number: DS25BR150

To mantain a protective buffer between a backplane connector and an FPGA using DS958.pdf to communicate, the DS25BR150 3.125 Gbps LVDS Buffer is almost a perfect fit. Unfortunately, the IC's maximum output common-mode voltage (1.375 V) puts it out of spec for LVDS15 (1.32 V). No resistive matching network (snla353.pdf ) can be implemented to move this common mode voltage down back into spec since the differential offset voltage minimum (250 mV) would also be proportionally brought down too much and therefore out of spec. Is there any differential signaling buffer IC (or collection of them) that meet the spec outlined by the FPGA in terms of common mode and differential offset voltage (data rate not considered and less important)?

  • +1
    TI__Genius 17506 points

    Hi Christian, 

    The TIA-644-A LVDS standard states the offset voltage of an LVDS driver will be 1.125V to 1.375V, which our buffers adhere to. It seems like this FPGA you are using isn't fully compliant with this standard. In this case, I would recommend AC-coupling the LVDS signals instead. You could add a lower DC bias after the caps via a resistor divider (see below), or you might be able to get away with just pure AC-coupled signals with no added DC bias since the datasheet you shared seems to have have a separate AC coupling common mode spec of 200-330mV. 

    Regards,

    Matt