TPS4816-Q1: schematic check

Part Number: TPS4816-Q1

Hi

Currently, power is not supplied; the FLT displays "low," and pins 16 and 13 are both "low." Please suggest where the schematic needs adjustment. Thanks

 

tps4816q1.pdf 

 

  • Hi Gareth, 

    Why would you expect pins 16 and 13 or FLT to be high if there is no voltage? 

    VIN must be HIGH to power your FLT pull up and device will also be off if VS < POR.

    Thanks,

    Sarah

  • Hi Sarah

    Sorry, let me explain. The input voltage is normal, but there's no output.

    Because Q2 lacks reverse connection protection, SRC is directly connected to the load, but the load has many capacitances, as shown in the red box in the diagram.

    What impact will this have?

    Thanks

  • Hi Gareth, 

    I see. The output capacitance alone shouldn't be an issue until you turn on. It will create a lot of INRUSH current. 

    If you are leaving the LPM and INP pins LOW, but getting a FLT this would be strange. Can you provide more information about the sequence of events? If FLT low automatically with a fresh VIN reset and LPM and INP low? 

    Thanks,

    Sarah

  • Hi Sarah

    The LPM and INP pins circuitry is designed to pull high. Even after pulling the jumper down, there is still no voltage applied. Measurements show UVLO = 3.9V and I2T = 0.5V when the input voltage is 20V. After removing the input voltage, FLT returns to high.

    Thanks

  • Hi Gareth, 

    I am looking at this now and will get back to you soon. 

    Thanks, 

    Sarah

  • Hi Sarah

    What exactly would cause a failure to conduct electricity?

    Thanks

  • Hi Gareth, 

    I'm confused by the circumstances again. 

    You say FLT return High when VIN is removed? Where is FLT pin voltage coming from? 

    If INP and INP_G are both low then there should be no current related FLT. 

    But now I am noticing you do have TMP setup, but I only see one resistor on TMP. This is expected to have an RNTC and RTMP value. Can you confirm you are using an NTC thermistor there? 

    You can try disabling TMP by floating TMP and directly GND ITMPO to verify if FLT_T is the issue. 

    Thanks, 

    Sarah

  • Hi Sarah

    Following your suggestion, I tried floating TMP and directly GND ITMPO.

    The test result showed that FLT was still LOW.

  • Can you also confirm the other questions? 

    Thanks, 

    Sarah

  • Hi Sarah

    It's still in a faulty, no-output state. I'll try the TPS4812 EVM later. Please let me know if you have any other suggestions or waveforms that need measuring.

  • Hi Gareth, 

    Yes, waveforms with OV and EN pin are helpful. 

    You can also get waveform with INP, LPM, BST-SRC, VGS, and with the input voltage. Adding the FLT pin transitions relative to these would be helpful as well as TMR and I2T pins to see if any current FLT are being recognized. 

    Thanks, 

    Sarah

  • Hi Sarah

    Measurement results are attached. Please assist in confirming. Thank you.

    TPS4816_20260807.pdf

  • Hi Gareth, 

    I am not finding precise explanation for FLT, but am seeing something odd here. 

    I assume your BST and SRC waveforms are mislabeled. If so it looks like the BST is charging before the EN pin actually reaches EN HIGH. Are you pre biasing the CBST? 

    Thanks, 

    Sarah

  • Hi Sarah

    Yes, the image label is incorrect.
    BST shows a sawtooth waveform, and SRC shows no voltage. The attached file shows the corrected waveform.
    Additionally, adjusting the timings of INP and INP_G also resulted in a sawtooth waveform for BST (as shown in the attached file).
    customer using a TPS4812 EVM. Shorting the reverse MOSFET (on R5 and R7) and soldering approximately 2000uF of capacitor to the output also resulted in a sawtooth waveform in BST. Adjusting the timings of INP and INP_G also yielded the same result. Are there any other parameters that need adjust?
    Thanks
  • Hi Sarah

    Are there any other parameters that you would like us to adjust?

    Thanks

  • I apologize for the delay. I will get back to you by mid week. 

    Thanks, 

    Sarah

  • Hi Gareth, 

    The FLT is going low as soon as the BST-SRC voltage reaches UVLOR which is when the gate is enabled. You are almost certainly seeing an INRUSH issue here. 

    The saw tooth on the BST pin is expected. Just indicates the charge pump is working. 

    Thanks, 

    Sarah

  • Hi Sarah

    Thank you for your comment. Do you have any suggestions for adjustments to INRUSH?

  • Hi Gareth, 

    You can use below example to help determine adequate slew controls. 

    You need to determine from your own system requirements what the turn on time needs to be. For this example lets assume 10us.

    I will be using the TPS1211 EVM and FET for this as well

     

    Use the capacitor charging equation I = C * dv/dt

    • C = FET input capacitance = Ciss = 15116 pF (typ)
    • Dv = V_BST (12V) – Vg,th (3V typ) = 9V
    • Dt = 10us

    Plugging in these values to above equation : I = 0.0136A

     

    This is the current required to limit the slew rate at GS. When considering the turn on of the FET, the gate  of our device has a strong 3.7A PU current. You can select a resistor to place at the gate in order to limit this to achieve required current/ turn on time (dt). Higher current = faster slew rate.

     

    The resistor value can be approximated, by assuming initial voltage at gate = 12V and I = 0.0136A, R = V/I :. R = 882 ohms. This will help you achieve 10 us turn on time.

     

    For our EVM design we selected 2.21 ohms + 10 ohms at the PU pin. Solving the same equation I = 12V / 12.21ohms = 0.983A. Solving the first equation for dt = C * dv/ I = 15116pF * 9V/0.98A = 0.138us.

     

    You can also consider a case where you only have the 2.2 ohm resistor at the gate. Here I = 12V/2.2ohm = 5.43A, but the internal FET PU is a strong current source that will limit the current to 3.7A maximum :. Our 2.2ohm selection would guarantee the fastest turn on time by avoiding limiting the current to the gate.

     

    You can also then calculate that the turn on time achieved here can be approximated with dt = C * dv/I = 15116 pf * 9V/3.7A = 0.003us. This is the fastest turn on time achieved with this particular FET.

     

    The resistor value 2.21 ohms is still valuable because it will also help dampen oscillations at the gate due to trace inductance. That is why we don’t just use 0ohms.

    Thanks, 

    Sarah

  • Hi Sarah

    Just to confirm, do you mean adjusting the values ​​of resistors R18 and R19 (470 ohms ~ 1kΩ) to force the MOSFET to remain on for a longer time?

    Thanks

  • No. R18 and R19 are only used to mitigate oscillations due to line inductance. 

    The resistor value 2.21 ohms is still valuable because it will also help dampen oscillations at the gate due to trace inductance. That is why we don’t just use 0ohms.

    I am talking about adjusting R25.

    Thanks,

    Sarah