Part Number: DP83822IF
I would like to clarify whether there may be any configuration or setting issues on the PHY side that could prevent 100BASE-FX communication.
- We designed a prototype using DP83822IF.
- We are currently debugging 100BASE-FX communication.
- Strap configuration has been verified and matches the intended design.
- The design is based on an existing 100BASE-TX implementation.
- 100BASE-FX communication does not work.
- Link-up indication via SD signal is confirmed.
- FX mode is confirmed to be enabled.
- Loopback testing based on the troubleshooting guide was performed.
- Loopback results are normal, indicating communication between CPU and PHY is working correctly.
- Therefore, there does not appear to be a configuration issue between CPU and PHY.
- Re-checked strap settings → confirmed correct.
- Performed loopback tests → passed.
- Since the design is based on a 100BASE-TX implementation, some configuration or register settings may not have been correctly adapted for 100BASE-FX operation.
- Are there any known differences or required configuration changes when transitioning from 100BASE-TX to 100BASE-FX on DP83822IF?
- Are there specific registers or initialization sequences that must be adjusted for proper FX operation?
- Are there any common pitfalls that could cause FX communication failure even when SD and link indicators appear normal?
Shota