TMDS1204: Invalid 4th lane

Hi,

Can you please share the I2C register dump?

Does the sink support HDMI1.4/2.0 clock and HDMI2.1 data on the same path or separate path? I see you are leaving RCLKOUTp/n floating in the schematic so I assume the sink can support clock and data on the same path, but can you confirm? If this is the case, do you enable or disable the fan out buffer?

Also, if you probe the input and output of lane 3 (4th lane?), do you see signal at both the input and the output?

Thanks

David

Hi David,

I have attached the register dump values.
-----TX Reg dump -------
-----------------------------
- TI_TMDS1204 I2C dump:
-----------------------------
     +0 +1 +2 +3 +4 +5 +6 +7
     ------------------------
00 : 54 4D 44 53 31 32 30 34
08 : 03 02 8E 43 70 22 97 00
10 : 02 0F 03 05 03 05 03 05
18 : 03 05 44 00 00 F3 00

The monitor which we are using is AW2725QF, which supports both legacy TMDS mode and FRL mode.
Yes, we have not connected the RCLKOUTp/n so the fan out buffer is disabled or enabled can be seen in I2C right? If we are testing in I2C mode?

Sorry but we dont have high bandwidth oscilloscope capable of probing 8Gbps.

Hi,

For register 0x09, can you please write 0x06 to it? This will force TMDS1204 to be always in active state.

For register 0x0A, why do you enable lane swap (bit 7) and disable DDC snooping? FAN out buffer is disabled (bit 6 = 0). If you disable the snooping, are you writing to register 0x20 and 0x31 for the correct HDMI rate?

Even without a 8G scope, you can still probe on the lane 3 to see if there is an output, and if there is an output, whether it is a clock or a data signal.

Thanks

David

Hi David,

We have made changes as mentioned below,
For register 0x09 it is changed to 0x06
For register 0x0A, we have disabled the lane swap and enabled Fan out buffer.

Still the 4th lane is invalid for all the resolution and no output for 4k @120 .

Could you please share any register value which you have used to validate this 2.1.

Below is the attached register set we use.

************************** Constant Definitions ******************************/

/**
* This table contains the values to be programmed to TI device.
* Each entry is of the format:
* 1) Device Type
* 2) Register Address
* 3) Values
*/
const Ti_RegisterField TiRegisterFields[] = {

  {TX_TI_R1_INIT, 0x0A, 0x4E}, //lanes swap 0x8E
  {TX_TI_R1_INIT, 0x0B, 0x43},
  {TX_TI_R1_INIT, 0x0C, 0x70},
  {TX_TI_R1_INIT, 0x0D, 0x22}, //was e3
  {TX_TI_R1_INIT, 0x0E, 0x97},
  {TX_TI_R1_INIT, 0x11, 0x0F},
  {TX_TI_R1_INIT, 0x09, 0x06}, // 02

  {TX_TI_TMDS_14_L_R1, 0x11, 0x00},
  {TX_TI_TMDS_14_L_R1, 0x0D, 0x22}, //was e3
  {TX_TI_TMDS_14_L_R1, 0x12, 0x03},
  {TX_TI_TMDS_14_L_R1, 0x13, 0x00},
  {TX_TI_TMDS_14_L_R1, 0x14, 0x03},
  {TX_TI_TMDS_14_L_R1, 0x15, 0x05}, // value
  {TX_TI_TMDS_14_L_R1, 0x16, 0x03},
  {TX_TI_TMDS_14_L_R1, 0x17, 0x05}, //value
  {TX_TI_TMDS_14_L_R1, 0x18, 0x03},
  {TX_TI_TMDS_14_L_R1, 0x19, 0x05}, //value
  {TX_TI_TMDS_14_L_R1, 0x20, 0x00},
  {TX_TI_TMDS_14_L_R1, 0x31, 0x00},
  {TX_TI_TMDS_14_L_R1, 0x11, 0x0F},

  {TX_TI_TMDS_14_H_R1, 0x11, 0x00},
  {TX_TI_TMDS_14_H_R1, 0x0D, 0x22}, //was e3
  {TX_TI_TMDS_14_H_R1, 0x12, 0x03},
  {TX_TI_TMDS_14_H_R1, 0x13, 0x00},
  {TX_TI_TMDS_14_H_R1, 0x14, 0x03},
  {TX_TI_TMDS_14_H_R1, 0x15, 0x05}, // value
  {TX_TI_TMDS_14_H_R1, 0x16, 0x03},
  {TX_TI_TMDS_14_H_R1, 0x17, 0x05}, //value
  {TX_TI_TMDS_14_H_R1, 0x18, 0x03},
  {TX_TI_TMDS_14_H_R1, 0x19, 0x05}, //value
  {TX_TI_TMDS_14_H_R1, 0x20, 0x00},
  {TX_TI_TMDS_14_H_R1, 0x31, 0x00},
  {TX_TI_TMDS_14_H_R1, 0x11, 0x0F},

  {TX_TI_TMDS_20_R1, 0x11, 0x00},
  {TX_TI_TMDS_20_R1, 0x0D, 0x22}, //was e3
  {TX_TI_TMDS_20_R1, 0x12, 0x03},
  {TX_TI_TMDS_20_R1, 0x13, 0x00},
  {TX_TI_TMDS_20_R1, 0x14, 0x03},
  {TX_TI_TMDS_20_R1, 0x15, 0x05}, // value
  {TX_TI_TMDS_20_R1, 0x16, 0x03},
  {TX_TI_TMDS_20_R1, 0x17, 0x05}, //value
  {TX_TI_TMDS_20_R1, 0x18, 0x03},
  {TX_TI_TMDS_20_R1, 0x19, 0x05}, //value
  {TX_TI_TMDS_20_R1, 0x20, 0x02},
  {TX_TI_TMDS_20_R1, 0x31, 0x00},
  {TX_TI_TMDS_20_R1, 0x11, 0x0F},

  {TX_TI_FRL_3G_R1, 0x11, 0x00},
  {TX_TI_FRL_3G_R1, 0x0D, 0x22},
  {TX_TI_FRL_3G_R1, 0x12, 0x03},
  {TX_TI_FRL_3G_R1, 0x13, 0x00},
  {TX_TI_FRL_3G_R1, 0x14, 0x03},
  {TX_TI_FRL_3G_R1, 0x15, 0x05}, // value
  {TX_TI_FRL_3G_R1, 0x16, 0x03},
  {TX_TI_FRL_3G_R1, 0x17, 0x05}, //value
  {TX_TI_FRL_3G_R1, 0x18, 0x03},
  {TX_TI_FRL_3G_R1, 0x19, 0x05}, //value
  {TX_TI_FRL_3G_R1, 0x20, 0x00},
  {TX_TI_FRL_3G_R1, 0x31, 0x01}, // 3gx3
  {TX_TI_FRL_3G_R1, 0x11, 0x0F},

  {TX_TI_FRL_6G_3_R1, 0x11, 0x00},
  {TX_TI_FRL_6G_3_R1, 0x0D, 0x22},
  {TX_TI_FRL_6G_3_R1, 0x12, 0x03},
  {TX_TI_FRL_6G_3_R1, 0x13, 0x00},
  {TX_TI_FRL_6G_3_R1, 0x14, 0x03},
  {TX_TI_FRL_6G_3_R1, 0x15, 0x05}, // value
  {TX_TI_FRL_6G_3_R1, 0x16, 0x03},
  {TX_TI_FRL_6G_3_R1, 0x17, 0x05}, //value
  {TX_TI_FRL_6G_3_R1, 0x18, 0x03},
  {TX_TI_FRL_6G_3_R1, 0x19, 0x05}, //value
  {TX_TI_FRL_6G_3_R1, 0x20, 0x00},
  {TX_TI_FRL_6G_3_R1, 0x31, 0x02}, // 6gx3
  {TX_TI_FRL_6G_3_R1, 0x11, 0x0F},

  {TX_TI_FRL_6G_4_R1, 0x11, 0x00},
  {TX_TI_FRL_6G_4_R1, 0x0D, 0x22},
  {TX_TI_FRL_6G_4_R1, 0x12, 0x03},
  {TX_TI_FRL_6G_4_R1, 0x13, 0x05}, //value
  {TX_TI_FRL_6G_4_R1, 0x14, 0x03},
  {TX_TI_FRL_6G_4_R1, 0x15, 0x05}, // value
  {TX_TI_FRL_6G_4_R1, 0x16, 0x03},
  {TX_TI_FRL_6G_4_R1, 0x17, 0x05}, //value
  {TX_TI_FRL_6G_4_R1, 0x18, 0x03},
  {TX_TI_FRL_6G_4_R1, 0x19, 0x05}, //value
  {TX_TI_FRL_6G_4_R1, 0x20, 0x00},
  {TX_TI_FRL_6G_4_R1, 0x31, 0x03}, // 6gx4
  {TX_TI_FRL_6G_4_R1, 0x11, 0x0F},

  {TX_TI_FRL_8G_R1, 0x11, 0x00},
  {TX_TI_FRL_8G_R1, 0x0D, 0x22},
  {TX_TI_FRL_8G_R1, 0x12, 0x03},
  {TX_TI_FRL_8G_R1, 0x13, 0x05}, //value
  {TX_TI_FRL_8G_R1, 0x14, 0x03},
  {TX_TI_FRL_8G_R1, 0x15, 0x05}, // value
  {TX_TI_FRL_8G_R1, 0x16, 0x03},
  {TX_TI_FRL_8G_R1, 0x17, 0x05}, //value
  {TX_TI_FRL_8G_R1, 0x18, 0x03},
  {TX_TI_FRL_8G_R1, 0x19, 0x05}, //value
  {TX_TI_FRL_8G_R1, 0x20, 0x00},
  {TX_TI_FRL_8G_R1, 0x31, 0x04}, // 8gx4
  {TX_TI_FRL_8G_R1, 0x11, 0x0F},

  {TX_TI_FRL_10G_R1, 0x11, 0x00},
  {TX_TI_FRL_10G_R1, 0x0D, 0x22},//22
  {TX_TI_FRL_10G_R1, 0x12, 0x03},
  {TX_TI_FRL_10G_R1, 0x13, 0x05}, //value
  {TX_TI_FRL_10G_R1, 0x14, 0x03},
  {TX_TI_FRL_10G_R1, 0x15, 0x05}, // value
  {TX_TI_FRL_10G_R1, 0x16, 0x03},
  {TX_TI_FRL_10G_R1, 0x17, 0x05}, //value
  {TX_TI_FRL_10G_R1, 0x18, 0x03},
  {TX_TI_FRL_10G_R1, 0x19, 0x05}, //value
  {TX_TI_FRL_10G_R1, 0x20, 0x00},
  {TX_TI_FRL_10G_R1, 0x31, 0x05}, // 10gx4
  {TX_TI_FRL_10G_R1, 0x11, 0x0F},

  {TX_TI_FRL_12G_R1, 0x11, 0x00},
  {TX_TI_FRL_12G_R1, 0x0D, 0x22}, //22
#if defined (XPS_BOARD_ZCU102)
  {TX_TI_FRL_12G_R1, 0x12, 0x02},
#elif defined (XPS_BOARD_ZCU106)
  {TX_TI_FRL_12G_R1, 0x12, 0x02},
#else //vcu118
  {TX_TI_FRL_12G_R1, 0x12, 0x03},
#endif
  {TX_TI_FRL_12G_R1, 0x13, 0x05}, //value
#if defined (XPS_BOARD_ZCU102)
  {TX_TI_FRL_12G_R1, 0x14, 0x02},
#elif defined (XPS_BOARD_ZCU106)
  {TX_TI_FRL_12G_R1, 0x14, 0x02},
#else //vcu118
  {TX_TI_FRL_12G_R1, 0x14, 0x03},
#endif
  {TX_TI_FRL_12G_R1, 0x15, 0x05}, // value
#if defined (XPS_BOARD_ZCU102)
  {TX_TI_FRL_12G_R1, 0x16, 0x02},
#elif defined (XPS_BOARD_ZCU106)
  {TX_TI_FRL_12G_R1, 0x16, 0x02},
#else //vcu118
  {TX_TI_FRL_12G_R1, 0x16, 0x03},
#endif
  {TX_TI_FRL_12G_R1, 0x17, 0x05}, //value
#if defined (XPS_BOARD_ZCU102)
  {TX_TI_FRL_12G_R1, 0x18, 0x02},
#elif defined (XPS_BOARD_ZCU106)
  {TX_TI_FRL_12G_R1, 0x18, 0x02},
#else //vcu118
  {TX_TI_FRL_12G_R1, 0x18, 0x03},
#endif
  {TX_TI_FRL_12G_R1, 0x19, 0x05}, //value
  {TX_TI_FRL_12G_R1, 0x20, 0x00},
  {TX_TI_FRL_12G_R1, 0x31, 0x06}, // 12gx4
  {TX_TI_FRL_12G_R1, 0x11, 0x0F},

  {RX_TI_R1_INIT, 0x0A, 0x4E}, //B}, // enabling RXOUTCLK
  {RX_TI_R1_INIT, 0x0B, 0x43},
  {RX_TI_R1_INIT, 0x0C, 0x70},
  {RX_TI_R1_INIT, 0x0D, 0xE3}, //E3
  {RX_TI_R1_INIT, 0x0E, 0x17}, //97
  {RX_TI_R1_INIT, 0x1E, 0x00},
  {RX_TI_R1_INIT, 0x11, 0x0F},
  {RX_TI_R1_INIT, 0x09, 0x02}, //00
  {RX_TI_R1_INIT, 0xF8, 0x03},

//  {RX_TI_TMDS_14_L_R1, 0x11, 0x00},
  {RX_TI_TMDS_14_L_R1, 0x0A, 0x4E}, //B}, // enabling RXOUTCLK
  {RX_TI_TMDS_14_L_R1, 0x0D, 0xE3},
  {RX_TI_TMDS_14_L_R1, 0x0E, 0x17},
  {RX_TI_TMDS_14_L_R1, 0x12, 0x03},
  {RX_TI_TMDS_14_L_R1, 0x13, 0x00}, //value
  {RX_TI_TMDS_14_L_R1, 0x14, 0x03},
  {RX_TI_TMDS_14_L_R1, 0x15, 0x05}, // value
  {RX_TI_TMDS_14_L_R1, 0x16, 0x03},
  {RX_TI_TMDS_14_L_R1, 0x17, 0x05}, //value
  {RX_TI_TMDS_14_L_R1, 0x18, 0x03},
  {RX_TI_TMDS_14_L_R1, 0x19, 0x05}, //value
  {RX_TI_TMDS_14_L_R1, 0x20, 0x00}, //2 was also working
  {RX_TI_TMDS_14_L_R1, 0x31, 0x00},
//  {RX_TI_TMDS_14_L_R1, 0x11, 0x0F},

//  {RX_TI_TMDS_14_H_R1, 0x11, 0x00},
  {RX_TI_TMDS_14_H_R1, 0x0A, 0x4E}, //B}, // enabling RXOUTCLK
  {RX_TI_TMDS_14_H_R1, 0x0D, 0xE3},
  {RX_TI_TMDS_14_H_R1, 0x0E, 0x17},
  {RX_TI_TMDS_14_H_R1, 0x12, 0x03},
  {RX_TI_TMDS_14_H_R1, 0x13, 0x00}, //value
  {RX_TI_TMDS_14_H_R1, 0x14, 0x03},
  {RX_TI_TMDS_14_H_R1, 0x15, 0x05}, // value
  {RX_TI_TMDS_14_H_R1, 0x16, 0x03},
  {RX_TI_TMDS_14_H_R1, 0x17, 0x05}, //value
  {RX_TI_TMDS_14_H_R1, 0x18, 0x03},
  {RX_TI_TMDS_14_H_R1, 0x19, 0x05}, //value
  {RX_TI_TMDS_14_H_R1, 0x20, 0x00},
  {RX_TI_TMDS_14_H_R1, 0x31, 0x00},
//  {RX_TI_TMDS_14_H_R1, 0x11, 0x0F},

//  {RX_TI_TMDS_20_R1, 0x11, 0x00},
  {RX_TI_TMDS_20_R1, 0x0A, 0x4E}, //B}, // enabling RXOUTCLK
  {RX_TI_TMDS_20_R1, 0x0D, 0xE3},
  {RX_TI_TMDS_20_R1, 0x0E, 0x17},
  {RX_TI_TMDS_20_R1, 0x12, 0x03},
  {RX_TI_TMDS_20_R1, 0x13, 0x00}, //value
  {RX_TI_TMDS_20_R1, 0x14, 0x03},
  {RX_TI_TMDS_20_R1, 0x15, 0x05}, // value
  {RX_TI_TMDS_20_R1, 0x16, 0x03},
  {RX_TI_TMDS_20_R1, 0x17, 0x05}, //value
  {RX_TI_TMDS_20_R1, 0x18, 0x03},
  {RX_TI_TMDS_20_R1, 0x19, 0x05}, //value
  {RX_TI_TMDS_20_R1, 0x20, 0x02},
  {RX_TI_TMDS_20_R1, 0x31, 0x00},
//  {RX_TI_TMDS_20_R1, 0x11, 0x0F},

//  {RX_TI_FRL_3G_R1, 0x11, 0x00},
  {RX_TI_FRL_3G_R1, 0x0A, 0x0E}, // disabling RXOUTCLK
  {RX_TI_FRL_3G_R1, 0x0D, 0xE3},
  {RX_TI_FRL_3G_R1, 0x0E, 0x17},
  {RX_TI_FRL_3G_R1, 0x12, 0x03},
  {RX_TI_FRL_3G_R1, 0x13, 0x05},//value
  {RX_TI_FRL_3G_R1, 0x14, 0x03},
  {RX_TI_FRL_3G_R1, 0x15, 0x05}, // value
  {RX_TI_FRL_3G_R1, 0x16, 0x03},
  {RX_TI_FRL_3G_R1, 0x17, 0x05}, //value
  {RX_TI_FRL_3G_R1, 0x18, 0x03},
  {RX_TI_FRL_3G_R1, 0x19, 0x05}, //value
  {RX_TI_FRL_3G_R1, 0x20, 0x00},
  {RX_TI_FRL_3G_R1, 0x31, 0x01}, // 3gx3
//  {RX_TI_FRL_3G_R1, 0x11, 0x0F},

//  {RX_TI_FRL_6G_3_R1, 0x11, 0x00},
  {RX_TI_FRL_6G_3_R1, 0x0A, 0x0E}, // disabling RXOUTCLK
  {RX_TI_FRL_6G_3_R1, 0x0D, 0xE3},
  {RX_TI_FRL_6G_3_R1, 0x0E, 0x17},
  {RX_TI_FRL_6G_3_R1, 0x12, 0x02},
  {RX_TI_FRL_6G_3_R1, 0x13, 0x05}, //value
  {RX_TI_FRL_6G_3_R1, 0x14, 0x02},
  {RX_TI_FRL_6G_3_R1, 0x15, 0x05}, // value
  {RX_TI_FRL_6G_3_R1, 0x16, 0x02},
  {RX_TI_FRL_6G_3_R1, 0x17, 0x05}, //value
  {RX_TI_FRL_6G_3_R1, 0x18, 0x02},
  {RX_TI_FRL_6G_3_R1, 0x19, 0x05}, //value
  {RX_TI_FRL_6G_3_R1, 0x20, 0x00},
  {RX_TI_FRL_6G_3_R1, 0x31, 0x02}, // 6gx3
//  {RX_TI_FRL_6G_3_R1, 0x11, 0x0F},

//  {RX_TI_FRL_6G_4_R1, 0x11, 0x00},
  {RX_TI_FRL_6G_4_R1, 0x0A, 0x0E}, // disabling RXOUTCLK
  {RX_TI_FRL_6G_4_R1, 0x0D, 0xE3},
  {RX_TI_FRL_6G_4_R1, 0x0E, 0x17},
  {RX_TI_FRL_6G_4_R1, 0x12, 0x02},
  {RX_TI_FRL_6G_4_R1, 0x13, 0x05}, //value
  {RX_TI_FRL_6G_4_R1, 0x14, 0x02},
  {RX_TI_FRL_6G_4_R1, 0x15, 0x05}, // value
  {RX_TI_FRL_6G_4_R1, 0x16, 0x02},
  {RX_TI_FRL_6G_4_R1, 0x17, 0x05}, //value
  {RX_TI_FRL_6G_4_R1, 0x18, 0x02},
  {RX_TI_FRL_6G_4_R1, 0x19, 0x05}, //value
  {RX_TI_FRL_6G_4_R1, 0x20, 0x00},
  {RX_TI_FRL_6G_4_R1, 0x31, 0x03}, // 6gx4
//  {RX_TI_FRL_6G_4_R1, 0x11, 0x0F},

//  {RX_TI_FRL_8G_R1, 0x11, 0x00},
  {RX_TI_FRL_8G_R1, 0x0A, 0x0E}, // disabling RXOUTCLK
  {RX_TI_FRL_8G_R1, 0x0D, 0xF3},
  {RX_TI_FRL_8G_R1, 0x0E, 0x17},
  {RX_TI_FRL_8G_R1, 0x12, 0x02},
  {RX_TI_FRL_8G_R1, 0x13, 0x05}, //value
  {RX_TI_FRL_8G_R1, 0x14, 0x02},
  {RX_TI_FRL_8G_R1, 0x15, 0x05}, // value
  {RX_TI_FRL_8G_R1, 0x16, 0x02},
  {RX_TI_FRL_8G_R1, 0x17, 0x05}, //value
  {RX_TI_FRL_8G_R1, 0x18, 0x02},
  {RX_TI_FRL_8G_R1, 0x19, 0x05}, //value
  {RX_TI_FRL_8G_R1, 0x20, 0x00},
  {RX_TI_FRL_8G_R1, 0x31, 0x04}, // 8gx4
//  {RX_TI_FRL_8G_R1, 0x11, 0x0F},

// {RX_TI_FRL_10G_R1, 0x11, 0x00},
{RX_TI_FRL_10G_R1, 0x0A, 0x0E}, // disabling RXOUTCLK
{RX_TI_FRL_10G_R1, 0x0D, 0xF3},
{RX_TI_FRL_10G_R1, 0x12, 0x02},
{RX_TI_FRL_10G_R1, 0x13, 0x00}, //value
{RX_TI_FRL_10G_R1, 0x14, 0x01},
{RX_TI_FRL_10G_R1, 0x15, 0x00}, // value
{RX_TI_FRL_10G_R1, 0x16, 0x00},
{RX_TI_FRL_10G_R1, 0x17, 0x01}, //value
{RX_TI_FRL_10G_R1, 0x18, 0x02},
{RX_TI_FRL_10G_R1, 0x19, 0x00}, //value
{RX_TI_FRL_10G_R1, 0x20, 0x00},
{RX_TI_FRL_10G_R1, 0x31, 0x05}, // 10gx4
// {RX_TI_FRL_10G_R1, 0x11, 0x0F},

//  {RX_TI_FRL_12G_R1, 0x11, 0x00},
  {RX_TI_FRL_12G_R1, 0x0A, 0x0E}, // disabling RXOUTCLK
#if defined (XPS_BOARD_ZCU102)
  {RX_TI_FRL_12G_R1, 0x0D, 0xF3}, //63}, //63
#elif defined (XPS_BOARD_ZCU106)
  {RX_TI_FRL_12G_R1, 0x0D, 0xF3}, //63
#else //vcu118
  {RX_TI_FRL_12G_R1, 0x0D, 0xF3}, //63
#endif
  {RX_TI_FRL_12G_R1, 0x12, 0x01}, //
#if defined (XPS_BOARD_ZCU102)
  {RX_TI_FRL_12G_R1, 0x13, 0x00}, //
#elif defined (XPS_BOARD_ZCU106)
  {RX_TI_FRL_12G_R1, 0x13, 0x05}, //
#else //vcu118
  {RX_TI_FRL_12G_R1, 0x13, 0x01}, //value
#endif
  {RX_TI_FRL_12G_R1, 0x14, 0x01}, //
  {RX_TI_FRL_12G_R1, 0x15, 0x01}, //
#if defined (XPS_BOARD_ZCU106)
  {RX_TI_FRL_12G_R1, 0x16, 0x00},
  {RX_TI_FRL_12G_R1, 0x17, 0x03}, //value
#else
  {RX_TI_FRL_12G_R1, 0x16, 0x01},
  {RX_TI_FRL_12G_R1, 0x17, 0x01}, //value
#endif

#if defined (XPS_BOARD_ZCU102)
  {RX_TI_FRL_12G_R1, 0x18, 0x02},
#elif defined (XPS_BOARD_ZCU106)
  {RX_TI_FRL_12G_R1, 0x18, 0x02},
#else
  {RX_TI_FRL_12G_R1, 0x18, 0x01},
#endif
  {RX_TI_FRL_12G_R1, 0x19, 0x01}, //value
  {RX_TI_FRL_12G_R1, 0x20, 0x00},
  {RX_TI_FRL_12G_R1, 0x31, 0x06}, // 12gx4
};

Regards,
Irfan

Irfan

Please see section 7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled as an example. You would want to disable the fan out buffer in this case. 

Are you able to get video out if you changed the resolution down to 4k@60Hz or 4k@30Hz? 

Thanks

David

Hi David,

The training is not finished completely. I noticed in log, that the Link Training Stage (LTS) was hanged at stage 2. It should finish the training, and the status should be shown as LTS: Pass. So, can we check whether the retimer is working properly to finish the training at 8Gbps per lane.

Are you able to get video out if you changed the resolution down to 4k@60Hz or 4k@30Hz?
Yes, but it is in TMDS mode it never switches to FRL.
Could you please tell how we can check that it is passing LTS.?

Regards,
Irfan

Irfan

1. The Sink set the SCDC register 0x41 and 0x42 to 0x00 to clear the link training pattern request

2. The Sink also set the FLD_UPDATE bit (bit 5) of the SCDC register 0x10, indicate that there is a change in register 0x41 and 0x42.

3. The Source will read the 0x41 and 0x42 and stop the link training pattern

4. The Source write to bit 5 of the SCDC register 0x10 to clear the FLD_UPDATE bit

5. The Sink set the FRL_START bit (bit 4) of the SCDC register 0x10, indicate training is completed

If you see link training is not completed, 

1. Change TMDS1204 into linear mode (Register 0x0D bit 7 = 1)

2. Tune TMDS1204 RX EQ at register 0x13, 0x15, 0x17, and 0x19

Or

1. Change TMDS1204 into limited mode (Register 0x0D bit 7 = 0)

2. Tune TMDS1204 RX EQ at register 0x13, 0x15, 0x17, and 0x19

3. Tune TMDS1204 TX VOD and De-emphasis at register 0x12, 0x14, 0x16, and 0x18

Thanks

David

Hi David,

I am unable to get you.
Could you please explain what is the issue and the solution what you have given can you please ellaborate this?

Thanks,
Irfan

Irfan

When you say "We tested multiple resolution but the 4th lane is still invalid for all resolutions and when we run 4k @120 fps the 4th lane is still invalid as before but there will be no output on the monitor." do you mean 4th lane (lane 3) has no output or signal quality of the lane 3 is bad that sink can't lock?

Assume that lane 3 has no output, then for this design

1. We need to make sure fan out buffer is disabled

2. Check and make sure there is signal present on lane 3 input and output

Assume that lane 3 has output but signal quality is bad, then

1. Please see my above response

2. It will be good to probe lane 3 output if possible while using the above tuning procedure to reduce the tuning time.

Thanks

David

Hi David,

When switched to FRL no lanes will be valid, all will show invalid now after the FRL Link training starts and it will fail.

Regards,
Irfan

Irfan

When you say no lanes will be valid, what does it mean? Does it mean no signal being received by the sink or there is a signal but the signal quality is bad?

Thanks

David

David,

Yes, there will no video output on the monitor but it will give output when it is set to TMDS

Regards,
Irfan

Irfan

I know you don't have a 8GHz scope, but do you have a scope, even lower bandwidth scope that can probe the TMDS1204 input when in FRL mode? 

No video output on the monitor could mean no signal or signal quality is bad, I am trying to differentiate between the two.

Thanks

David

Hi David,

Please find the attached log for FRL. When I disconnect and reconnect the HDMI cable, the FRL Link Training progresses to Stage 3.

Thanks,
Irfan

HDMIPHY log
------
TX TMDS Reconfig
TX frequency event
QPLL lost lock
TX frequency event
TX frequency event
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
TX MMCM lock
QPLL lock
TX reset done
TX alignment done
TX frequency event
QPLL lost lock
TX TMDS Reconfig
Error!  TX: Line rates > 8.0 Gbps are not supported by -1/-1LV devices
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
TX MMCM lock
QPLL lock
TX reset done
TX alignment done
TX FRL Reconfig


HDMI TX log
------
Stream is Down
TMDS Start
Set Stream
Stream is Down
Audio Unmuted
Set Audio Channels (2)
Stream Start
Stream is Up
VID Bridge Locked
Cable is disconnected....
VID Bridge Unlocked
Stream is Down
Cable is connected....
FRL Start Training (MaxFrlRate: 6)
FRL Config
FRL LTS:2 (FRL_Rate: 10 FFE_Levels: 0)
FRL LTS:3 (LTP: 0x5)
FRL LTS:3 (LTP: 0x6)
FRL LTS:3 (LTP: 0x7)
FRL LTS:3 (LTP: 0x8)
FRL LTS:3 (Rate Drop Requested)
FRL LTS:4 (FRL_Rate: 8 FFE_Levels: 0)
FRL Config

------------
Additional Info
------------
System Status
------------
VsyncCounter: 19646
TX HW AUX FULL Counter: 0
------------
Bridge Status
------------
TX BRIDGE OVERFLOW ,0
TX BRIDGE UNDERFLOW ,0
SCDC status : 40
------------
Error Detection Status From Sink
------------
Channel 0 CED: Invalid
Channel 1 CED: Invalid
Channel 2 CED: Invalid
Channel 3 CED: Invalid
RSED: Invalid
------------
System: IP Version
------------
HDMI TX SS
------------
  ->HDMI TX Subsystem Cores
    : HDMI TX
No VTC Configuration, No Video Clock!
  HDMI TX version : 01.00 (0800)
  VTC version is not available for reading as HDMI TX Video Clock is not ready.

------------
TX Core Status
------------
CORE_VER_PUB, INT: 0x1000800, 0xB
ADD_CORE_DBG: 0x0
FRL_MODE, LANES: 1, 1
HDMI/DVI MODE: 1
FRL_LCKE_OOS: 0
FRL_LCKE_FREQ(Khz): 0
FRL_EXT_VCKE: 0
FRL_VCKE_FREQ(Khz): 0
FRL_VCKE_FREQ(Measured Khz): 400000
TX Bridge Locked: 0
NTV_ANLZ_TIM_CHG (add_core_dbg=1): 0
TRIB_ANLZ_TIM_CHG (add_core_dbg=2): 0
FRL_ANLZ Video Timing (add_core_dbg=3)
  TIM_CHG: 0
  HS, HBP, ACT, LN: 0, 0, 0, 0

-----
Info
-----

------------
HDMI TX SubSystem
------------
HDMI TX timing
------------
HDMI TX Mode - HDMI FRL (4 lanes @ 8 Gbps)
HDMI Video Mask is Disabled

        Color Format:             RGB
        Color Depth:              8
        Pixels Per Clock:         8
        Mode:                     Progressive
        DSC Status:               Uncompressed
        Frame Rate:               60Hz
        Resolution:               1920x1080@60Hz
        Pixel Clock:              148500 kHz

        HSYNC Timing: hav=1920, hfp=88, hsw=44(hsp=1), hbp=148, htot=2200
        VSYNC Timing: vav=1080, vfp=04, vsw=05(vsp=1), vbp=036, vtot=1125
VIC: 16
Scrambled: 0
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
ACR CTS  : 9732
ACR N    : 6144
Static HDR DRM Infoframe
---------
No DRM info

------------
HDMI PHY
------------
GT status
---------
TX reference clock frequency: 148502528 Hz
TX: QPLL0
TX state: ready

QPLL0 settings
-------------
M : 1 - N : 80 - D : 2

TX MMCM settings
-------------
Mult : 15 - Div : 4 - Clk0Div : 4 - Clk1Div : 4 - Clk2Div : 4

Irfan

Have you tried these two yet and see if it makes an impact to the link training?

If you see link training is not completed, 

1. Change TMDS1204 into linear mode (Register 0x0D bit 7 = 1)

2. Tune TMDS1204 RX EQ at register 0x13, 0x15, 0x17, and 0x19

Or

1. Change TMDS1204 into limited mode (Register 0x0D bit 7 = 0)

2. Tune TMDS1204 RX EQ at register 0x13, 0x15, 0x17, and 0x19

3. Tune TMDS1204 TX VOD and De-emphasis at register 0x12, 0x14, 0x16, and 0x18

Any chance you can send a system to me?

Thanks

David