DS90UB947-Q1EVM: DS90UB947-Q1EVM: How t configre Dual OLDI mode (Continued)

Nicholas-san,

Thank you for your understanding.
I attempted to use the UB947/948EVM setup to transmit Dual OLDI signals—output
from an FPGA—to an LDC panel connected to the UB948 output, maintaining the clock
in "ASIS" mode. However, the result was unsuccessful.

As I mentioned in my previous inquiry, the output pixel clock frequency was
half that of the input clock.

Could I ask a favor?

Using the UB947/948EVM you have on hand, could you configure the device
for Dual OLDI input and Dual OLDI output modes and verify that the input
clock is output in ASIS mode?

Video data is not required; please let me know the configuration needed
to output the clock in ASIS mode.

Mita

Hi Mita,

Niko and I are not familiar with what ASIS mode is. Can you please share what that means? 

BR,

Esther

Esther-san,

ASIS means "As it is"

Mita.

Hi Mita,

Sorry, is this what you're seeing on your setup? Or something different?

This will help me understand what to set up in the lab. 

BR,

Esther

Esther-san,

Thank you for your reply.
The diagram you sent is correct.
However, as the bandwidth of the oscilloscope I have on hand is insufficient,
I have not verified the data rate between the UB947 and the UB94.

Please verify this in the lab.

Here is a report on the findings from my investigation yesterday.

The UB947EVM manual states that the Single/Dual OLDI input mode can be switched
by changing the S2 setting.
I attempted to switch between Single and Dual OLDI inputs by turning on SW2,
S1, or S5, but I was unable to switch to Dual OLDI mode.

Further investigation yielded the following results: settings S1 through
S6 operated in Single OLDI mode, while S7 and S8 operated in Dual OLDI mode.
This determination was made by checking the status of Register 0x4F, Bit 6,
and verifying the input/output clock frequencies.

The Mode pin voltages for each S2 setting were as follows:

1: 0V
2: 0.374V
3: 0.576V
4: 0.766V
5: 0.970V
6: 1.186V
7: 1.405V
8: 1.744V
Vdd1R8 = 1.814V

Mita

Hi Mita,

Thanks for the details. I want to reiterate that this expected behavior in dual mode. 

What would you like the CLK to be instead? 

user4779049 said:

Further investigation yielded the following results: settings S1 through
S6 operated in Single OLDI mode, while S7 and S8 operated in Dual OLDI mode.
This determination was made by checking the status of Register 0x4F, Bit 6,
and verifying the input/output clock frequencies.

Yes, MODE_SEL0 should only have 4 options. This is from the datasheet - 

The table is outdated in the EVM user guide. Sorry about that. 

BR,

Esther

Esther-san

Thank you for your reply.

I am aware that the table below is included in the datasheet.

Could you please set the evaluation board to settings 1 and 5
in this table and check the respective clock frequencies?

Registered address 0x4B bit 5 indicates the result of Single/Dual
OLDI In being selected. Please check if this bit changes depending
on the Mode setting when you switch modes.

Setting 1 is Single OLDI In, Dual OLDI OUT, so it corresponds
to the diagram you sent (Figure 1).

                                 Figure 1

When set to 5, it's Dual OLDI In, Dual OLDI OUT, so I expect
it to look like the diagram below (Figure 2).
However, the reality is as shown in the diagram above (Figure 1).

                          Figure 2

Mita

Hi Mita,

There seems to be a confusion between dual and single-pixel OLDI in on the 947. Regardless of dual or single-pixel strap on MODE_SEL0 of the 947, the CLK will be the same as your clock source. It just distributes the data differently. When you are in single-pixel OLDI in, then data will be distributed through D0-D3. When you are in dual-pixel OLDI in, then data will be distributed through D0-D7. 

single-pixel OLDI in on 947

dual-pixel OLDI in on 947

If the LMK03328 is driving a clk of 150 MHz, this would be the expected value regardless of whether the UB947 is in single or dual pixel mode and the UB948 is set to dual OLDI output. 

I hope this clears up the confusion.

BR,

Esther

Esther-san

Here is a simple request.

1. Set SW2 on the UB947 evaluation board to S1 On.
2. Input a 75MHz LVDS clock to the UB947 evaluation board.
3. Measure the frequency of the LVDS clock on the UB948.
4. Check the state of Address 0x4F bit6 on the UB947 evaluation board.
5. Invert the state of Address 0x4F bit6 on the UB947 evaluation board.
6. Measure the frequency of the LVDS clock on the UB948.
7. Report me the results.

Mita

Hi Mita,

Sorry, just got to this now. In my testing, the 948 output is set to Dual OLDI and I'm driving 947 CLK with 75 MHz.

When 947 SW2 is set to dual-pixel, the output CLK1+ on 948 is half the frequency - 37.5 MHz. 

When I invert the state to single-pixel, the output CLK1+ on 948 is the same frequency - 75 MHz. 

BR,

Esther

Esther-san,

Thank you for your reply and testing the evaluation board.

Please let me know the results of Steps 4 through 6 of the
test procedure I previously requested.

4. Check the address state of bit 6 at 0x4F on the UB947 evaluation board.
5. Invert the state of bit 6 at address 0x4F on the UB947 evaluation board.
6. Measure the frequency of the LVDS clock of the UB948.

Mita

Hi Mita,

No problem. My testing today included those steps. I inverted the state of bit 6 from dual to single-pixel to measure the 948 CLK. 

BR,

Esther

Esther-san,

Thank you for your prompt reply.

When SW2's S1 was turned ON, was the value of Address 0x4F bit 6 '1'
or '0'?

When SW2's S5 was turned ON, was the value of Address 0x4F bit 6 '1'
or '0'?

Please note that when switching SW2's S1 and S5, you need to turn
the evaluation board's power OFF/ON once.

Mita

Hi Mita-san, 

user4779049 said:

When SW2's S1 was turned ON, was the value of Address 0x4F bit 6 '1'
or '0'?

1 (single-pixel).

user4779049 said:

When SW2's S5 was turned ON, was the value of Address 0x4F bit 6 '1'
or '0'?

Also 1 (single-pixel).

Thanks for catching this, I need to look into why the datasheet states that S5 is dual mode. 

BR,

Esther

Esther-san,

I am glad you noticed.
I would appreciate it if you could let me know the
recommended procedure for switching to "duaru OLDI" input mode.
I look forward to your reply.

Mita

Hi Mita-san,

Upon further investigation, it looks like you need to PDB the EVM (S4) to get into the proper mode. After setting the MODE_SEL0 = 5 and powering on, please try PDB-ing the EVM and check the result. Based on my testing, it should go into dual mode. 

BR,

Esther

Esther-san,

Thank you for your response.

Yes, after changing the Mode 1 configuration switch (SW2) settings,
I powered the evaluation board off and then back on.

However, the results you provided do not match my observations.

In my testing, the device operated in Dual OLDI Mode only when either
S7 or S8 was turned on.

When I turned on any of S1 through S6 and power-cycled the evaluation
board (OFF → ON), the device did not enter Dual OLDI Mode.

Could you please double-check this once again?

Thank you for your support.

Best regards,

Mita

Esther-san,

Thank you for your reply.

So, in your tests as well, the settings did not take effect
as expected when cycling the power (Power Off/On).

It seems likely that the relationship between the power-up
time and the timing of the strap pin sampling is the cause.

I would like to test this on our end as well.
However, I do not currently have an evaluation board
available, so I will not be able to perform the verification
for a few weeks.

Therefore, I will close this case for the time being.

Thank you for your continued assistance with this issue
over such a long period.

Mita

Esther-san,

Thank you for your reply.
I truly appreciate the sincere way you answered my
persistent questions.
I, too, look forward to working with you.
Have a wonderful day.

Mita