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Original question:

DP83867IR: DP83867 PHY Address Strapping Issue

DP83867IR: DP83867IR Phy Address Strapping Issue

Joseph Romeo
Prodigy 20 points

Part Number: DP83867IR

It looks like the following support ticket was closed and I am unable to post replies so following up here on it https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1630033/dp83867ir-dp83867-phy-address-strapping-issue/6300962. 

I have some additional experiments that I performed but will share that in a future comment, but wanted to clarify the requirements of the power up sequence. In the www.ti.com/.../dp83867ir.pdf datasheet, I see the requirement that the 1.8V supply should be stable within 25ms of the 2.5V supply coming up, but that it can come up anytime before the 2.5V rail.

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I found this additional information "Make sure to supply VDDIO1P8 after VDDA2V5" from the troubleshooting guide which I believe was added after my previous forum post:

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In our circuit, our VDDIO1P8 and VDDA1V8 share the same source, and we have the 1.8V rail (both VDDA and VDDIO) coming up before the 2.5V rail. What are the potential issues that could follow supplying VDDIO1P8 before VDDA2V5?

  • 0
    TI__Mastermind 38705 points

    Hi Joseph,

    The potential issue with supplying 1.8V before 2.5V is slight back-powering of the 2.5V rail. So you may see a leakage voltage coming from 2.5V if 1.8V comes up first. 

    This typically isn't an issue for the DP83867 itself, however it could affect other devices attached tot he 2.5V rail if they are not expecting this leakage voltage. This is why the following note is in the datasheet:

    Best,

    Shane