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PCIe problem (C6678L => XIO2200)

göksel günlü
Intellectual 300 points 



In our project we want to communicate C6678L and Xio2200 boards. 
to be ensure there is no hardware or software problem for each board, we realized two experiment.
Firstly, two c6678L board succesfully communicated through AMC connectors. 
"PCIe example project" is loaded to each board, one board configured as root complex, other end point.
Secondly xio2200 board connected two a PCIe slot of a PC. then using "ohcirom", xio2200.dat file succesfully loaded into EEPROM.
This two experiment shows that, two boards runs succesfully. 
However we couldn't communicate C6678L and xio2200 with eachother, program hang out at "link training" step. 

Note: C6678L couln't supply 100Mhz referans clock(CLK_P and CLK_N ) to XIO2200 through AMC connector. 
Therefore we used ICS512 PLL and 25Mhz XTAL to generate 125Mhz single clock for XIO2200.
  • 0
    TI__Guru* 76130 points

    Hello,

    Make sure your REFCLK meets all the specifications , specially the jitter parameters. See the PCI Express Jitter and BER White Paper from the PCI-SIG.

    Connect a pull-up to 3.3V on terminal REFCLK_SEL.

    Connect a capacitor from REFCLK- to Vss.

    Follow the Power-up sequence described on section 3.1.1 of datasheet(at the link below)

    Regards.

    http://www.ti.com/lit/ds/scps154c/scps154c.pdf

  • 0 in reply to Elias Villegas M.
    Intellectual 300 points

    Thank You Villegas,

    I have read datasheet several times, and

    connected REFCLK_SEL to 3.3V.

    connected a capacitor from Refclk - to Vss

    followed the power up sequence. reset XIO by using GPIO of the 6678.

    Howevver I couldn't test jitter parameters, I used ICS 512 and 25Mhz XTAL. Do you have any suggestion for the clock. Could we configure 6678 as differential clck source for XIO2200  (datasheets says no)

    (Program in the 6678L configures as root complex and gen1)

    Regards

    Goksel

  • 0 in reply to göksel günlü
    TI__Guru* 76130 points

    Hello Goksel,

    Are you using a XIO2200 Evaluation module?

    Do you have series capacitors on the PCIe TX+/- lines of the XIO2200? what value are these?

    Can you provide scope captures of the REFCLK, RESET Vs Power. Also a register dump and the schematics will help.

    Regards.

  • 0 in reply to Elias Villegas M.
    Intellectual 300 points

    Hello Villegas,

    *********Are you using a XIO2200 Evaluation module?

    we used our board which i copied from XIO2200 Evaluation module. We test the board PC. it succesfully write EEPROM using Ohcirom.

    ********Do you have series capacitors on the PCIe TX+/- lines of the XIO2200? what value are these?

    We add 100nf capacitor to XIO2200 RXp and RXn input. I think there is a design problem in c6678L evaluation board. 100nF couplaj capacitor should be on the  TX lines, not RX lines. If we connect AMC connector of C6678L and PCIe connector of XIO2200, there will be two 100nf couplaj capacitor on the XIO_TX and C6678L RX line. we removed couplaj capacitors on theTX line of the XIO2200, Since there are couplaj capacitors on the RX line of the C6678 .

    ******** Can you provide scope captures of the REFCLK, RESET Vs Power. Also a register dump and the schematics will help.

    Refclk generated by ISC512 which powered from XIO2200 3.3V line. when XIO2200 is powered, clk is started to generate clk . We connected C6678L GPIO15 pin to #PERST input of the XIO2200. First C6678 assert low to #PERT, then XIO2200 evaluation board is powered, after waiting 3 sec, C6678 configures PCIe and start link training. But link training failed.

    I have attached schematics we used.

    Best Regards

    goksel

    FIREWIRE.pdf
  • 0 in reply to göksel günlü
    TI__Guru* 76130 points

    Hello Goksel,

    By specification all the PCIe transmitters has to be AC coupled.

    Please connect the 0.1uF series capacitors only in the TX lines of the XIO2200 and on the TX lines of the c6678L and close to the PCIe connector of each transmitter.

    Regards.