DVI to LVDS converter

Hi Raju, see these documents.  The second one isn't for the TFP401A-EP exactly, but it still applies.

http://www.ti.com/litv/pdf/slla325
http://focus.ti.com/lit/an/slla134/slla134.pdf

Best regards,
RE

Hi RoosE,

Thanks for the reply.

I assume, TFP401A-EP and SN75LVDS83B combination will be suitable for my LCD panel (LP154W01-A5).

Could you please confirm on this.

Thanks,

Raju

Appala,

I will defer to Ross on the technical aspects on if the combination will work with your panel.

However, I noticed you are using the -EP version of the TFP410A.  This is the enhanced plastic package typical for hi-reliability applications (speced for -55 to +125C operation).  The SN75LVDS83B is only speced for commercail temperature (0 to +70 C) operation so from a "temperature" basis, this seems to be a mis-match,  If you need extended temperature range, the SN65LVDS93A is the same functionality and performance as the LVDS83B, only it is speced for industrial temperature (-45 to +85 C operation).  On the other hand if commercial tempearture is fine, then the TFP410A is available in commercial temperature options for less than half the cost.

Hi RossE,

Thanks for the clarification. I will go with chips which supports commercial temperature range.

I have prepared schematic for this HDMI/DVI to LVDS Bridge. Here I attached document.

Could you please review it and provide me your suggestions or modifications.

Thanks,

Raju.

Hello Raju,

I have reviewed the schematic and found two issues:

1) /STAG pin on the TFP401A should be tied high.
2) Since they are selecting OCK_INV=low on the TFP401A, they should also connect CLKSEL=low on the LVDS83B.

Also, please check the document on the below link for design recommendations.

Regards.

http://www.ti.com/lit/an/slla136/slla136.pdf

Hi ELIAS VILLEGAS,

Thanks for the reply.

1) Connected STAG# to VCC_3.3V through 10K resistor.

2) Pulled down CLKSEL to ground through 1K resistor.

I used NXP "PCA9633DP1" IC as Back-light controller.

Is there any IC from TI, which suitable for the same operation?

I found "TLC59108F". But, LED control outputs are Active low and I looking for Active high.

Could you please suggest me the suitable IC from TI.

Thanks,

Raju.

Hi ELIAS VILLEGAS,

May I have any update on this.

Thanks,

Raju.

Hello Raju,

I am not familiar with back light controllers, but you may want to visit the below link.

Regards.

http://www.ti.com/product/ucc25710

Hi ELIAS VILLEGAS,

After long time, I am posting question on this again. Sorry for the long gap

From Design recommendation document (http://www.ti.com/lit/an/slla136/slla136.pdf), we should use 22uF, 0.01uF capacitors for DVDD, OVDD, AVDD and PVCC.

But I used 10uF, 0.01uF capacitors. Based on following document.

http://www.ti.com/lit/an/slla134/slla134.pdf

Could you please confirm on this. I mean, need to change my design or I can go with it.

Thanks,

Raju.

There should be not a big issue.

Regards.

Hi Elias Villegas,

What are specification for Ferrite beads which are user to connect to OVDD, AVDD, DVDD and PVDD pins on TFP401A IC.

Thanks,

Raju.

That usually depends on the power supply used, but the evaluation module for the TFP401 uses a 600ohm, 200mA @100MHz ferrite bead.

Regards.

I used 3.3V to connect these pins.

Shell I proceed with 600ohm, 200mA @100MHz ferrite bead?

Well, I was talking more about the quality of the power supply, but yes, I think that ferrite bead should be fine.

Regards.

Hi Elias Villegas,

I think, I made a mistake in schematic.

"PIXS", pin-4 tied to VCC through 10k resister and using QE[23:0] pins only used to connect to LVDS transmitter (SN75LVDS83B) data input pins D0 to D17.

If "PIXS" is high, RGB data will be split odd/even on QO[23:0] and QE[23:0].

Can you please correct me on this.

Here I am attaching schematic again.

Could you please kindly re-review it again.

Thanks,

Raju.

Hi ELIAS VILLEGAS,

May I have any update on this.

Thanks,

Raju.

Hello Raju,

Your assumption is correct.

When PXIS=3.3V then the even pixels will be output on QE[] and the odd pixels on QO[].

When PIXS=Gnd, both even and odd pixels will be output on QE[] sequentially starting with pixel #0.

Your schematic looks correct, I am just not sure on the bit mapping on the LVDS83B, can you send the panel datasheet to see what is the required bit sequencing?

Regards.

Hi ELIAS VILLEGAS,

Here I am attaching LCD data sheet. Please find it as an attachment.

As per LCD data sheet, I need to tie PIXS to GND.

Could you please confirm this.

Thanks,

Raju.

Yes, connect PIXS to gnd.

Another comment, the LCD only has 6-bit color dept, so you only need 18bpp.

See Figure 15 in the SN75LVDS83B datasheet for a reference configuration.

Regards.

So, both even and odd data pixels must be on QE data bus only.

Yaa my LCD needs only 18-bit (6 X 3) of data.

I followed Figure 17 in the SN75LVDS83B datasheet for improved image quality.

In future, I may go for 24-bit (8 X 3) LCD by using Y3M and Y3P signals of SN75LVDS83B.

Hi Elias,

The timing requirements seem to be not met to connect the TFP401 and the SN75LVDS83B.

The data setup time of TFP401 is shorter than the data setup time of SN75LVDS83B. The data setup time to ODCK clock edge on TFP401 is 1.8ns (PIXS=low, OCK_INV=low), but the data setup time before CLKIN clock edge on SN75LVDS83B is 2ns.

The data hold time of TFP401 is shorter than the data hold time of SN75LVDS83B. The data hold time from ODCK clock edge on TFP401 is 0.6ns (PIXS=low, OCK_INV=low), but the data hold time after CLKIN clock edge on SN75LVDS83B is 0.8ns.

Can the timing requirements be met?

Best regards,

Daisuke

Hi,

There is my new post here: http://e2e.ti.com/support/interface/high_speed_interface/f/138/t/381898.aspx

Best regards,

Daisuke