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TLK3101

Sergei Shishanov
Prodigy 40 points


Hi.
I use TLK3101 chip for transmiting 2.5 Gbps signal. When I set LOOPEN=1, I saw out signal equal input signal (internal loop back). Next I set LOOPEN=0, PRBSEN=0, ENABLE=1, LCKREFN=1,
TX_EN=1, TX_ER=0 and set external loop back (locked input and output). GTX_CLK=125MHz. I saw RX_CLK 2.3V, 125MHz,  RX_DV=1 and RX_ER=1(sometimes 0 - random) - out signal not equal input. Why?  
What about sinchronization? I don't understand about it.

Best regards.
Sergey.

  • 0
    TI__Mastermind 20820 points

    Hi Sergay,

    The TLK3101 has a comma detect circuit on the RX side that is looking for a comma character (K28.5) to align the data and RX_CLK to. Because you are seeing the RX_ER toggle between 1 and 0 my initial thought is that the TLK3101 is receiving the K28.5 character and locking to it sometimes but other times it is not. Are you saying that sometimes the TLK3101 locks and runs properly and other times it does not lock? Or is the device locking and then losing lock after it is established?  

    To answer your question about synchronization:

    When parallel data is clocked into a parallel to serial converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data. When the serial data is received and converted to parallel format again a way is needed to be able to recognize the byte boundary again. Generally this is accomplished through the use of a synchronization pattern. This is generally a unique pattern of 1s and 0s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8-bit/10-bit encoding contains a character called the comma (b’0011111’ or b’1100000’) which is used by the comma detect circuit on the TLK3101 to align the received serial data back to its original byte boundary. The decoder detects the K28.5 comma, generating a synchronization signal aligning the data to their 10 bit boundaries for decoding. It then converts the data back into 8 bit data, removing the control words. The output from the two decoders is latched into the 16 bit register synchronized to the recovered parallel data clock (RX_CLK) and the output is valid on the rising edge of RX_CLK.

    Let me know if this is not clear and I can elaborate more.

    Regards,

    Mike