Hi guys,
I submitted this question to TI support, but they directed me to post any support requests here to the forum.
I am trying to use a 20GHz clock rate, 3-bit plus over-range, ADC from Hittite. The ADC performs 1:2 demux, so the output data stream is 10Gbps.
The ADC uses negative voltage power rails, so the output CML have a negative common mode. I plan to process data from the ADC using Altera Stratix IV GT FPGAs, so these lanes need to be AC-coupled to the FPGA. I'd like to place the ADC on a different board than the FPGA, and connect them together using QSFP+ cabling. The DS100RT410 or any of the redriver devices could be used for this application.
To AC couple the signals from the ADC to any other device requires that the signal coming from the ADC has no DC bias. The ADC has an XOR input port that allows a PRBS pattern to be XORed onto the ADC data, thus ensuring enough data transitions. In the attached diagram, I show how a DS100RT410 could potentially be used as the PRBS source; the ADC 10GHz output clock would be divided to create a 10Gbps 0,1,0,1... data stream and the DS100RT410 configured in lock-to-data mode to be synchronous to the ADC clock. The output would be configured for PRBS mode to 'spread' the ADC data.
Does this design seem reasonable?
Are parts available? I'd like to get 5 to 10 pcs so that I can add them to an ADC test board to see if this is feasible.
Cheers,
Dave