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TCA9517 - About usage of TCA9517

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Guru 21045 points
Other Parts Discussed in Thread: TCA9517

My customer wants to make VOL small using TCA9517.

Is TCA9517 usable by the circuit of page2 of the attached file ?

And, is TCA9517 usable by the circuit of page3 of the attached file?

please give me advice.

 

<My guess>

I think that the circuit of page2 is usable.

=>datasheet P9 “Master devices can be placed on either bus.”

 

I think that the circuit of page3 is not usable.

=>datasheet P2 “The TCA9517 cannot be connected B side to B side”

 

 

<Background>

By the usage of my customer, the SDA/SCL line has many noises.

(The noise is adverse effects of the cables.)

Therefore,The low level output voltage(VOL) of TAC9517 may become higher than "Low level input voltage(VIL=0.99V)" of the Slave device.

(the circuit of page1 of the attached file)

So my customer intends to prevent the adverse effects of the noise by making VOL small.

・TCA9517 1chip Circuit VOL = 0.6V (attached file page1) => now

・TCA9517 1chip Circuit VOL = 0.2V (attached file page2) => in review 1 (My idea)

・TCA9517 2chip Circuit VOL = 0.2V (attached file page3) => in review 2 (My customer idea)

 

Regards,

Kanemaru

20130520　TCA9517 circuit .pdf
  • 0
    TI__Intellectual 2020 points

    Kanemaru-san,

    You are correct the TCA9517 cannot be used B-side to B-side as the customer suggested on page3. On top of this it is best to use the TCA9517 in a configuration where VCCB is greater than or equal to VCCA.

    This means that the best option for this application is your suggestion from page2. The customer will just need to make sure that the VOL of the master can support the input logic levels of the B-side. This is the VILC spec on the datasheet of 0.4V seen below

    This means as long as VOL max of the master (for the application IOL) is less than or equal to 0.4V the suggestion from page2 will work correctly.

    Regards
    Chris Kraft 

  • 0 in reply to Chris Kraft
    Guru 21045 points

    Hi,Chris

     

    Thank you for the information.

    I have three questions I want to ask.

     

    [Q1]

    When I connected B-side and B-side, does the TCA9517 malfunction?

    Please tell me the operation of TCA9517.

     

    [Q2]

    When I use TCA9517 under conditions of "VCCB < VCCA", does the TCA9517 malfunction?

    Please tell me the reason why you recommend a condition of "VCCB >= VCCA".

     

    [Q3]

    Is there your idea except the page2 of attached file?

    (“TCA9517 + other device” etc...)

     

    When my customer connects b-side of TCA9517 and Master*, a communication error occurs.

    *Master is HDIM device(DDC signnal)

     

    Regards,

    Kanemaru

  • 0 in reply to Hide
    TI__Intellectual 2020 points

    Hi Kanemaru-san

    Sorry for the delay.

    [Q1]: To ensure that the B-side drives the A-side low, the voltage input into the B-side must be less than VILC - 0.4V. And to enusre that the device does not lock-up the I2C bus th when the A-side drives the B-side low, the B-side will only output a VOL level of 0.52V typical. This means that a low level out on the B-side will not register as a low level in when the two B-sides are tied togther. This is why the device cannot be used B-side to B-side

    [Q2]: The TCA9517 is powered off of the VCCB rail and the VCCA rail is just used as a reference level for the A inputs. This is why we always recommend that VCCB (main supply voltage) is higher than the VCCA side.

    [Q3]: Is the master VOL less than VILC (0.4V)? Does the customer have any scope shot of the failure and a schematic of the design? This would help greatly in determining why they are seeing a communication error.

    Regards,
    Chris Kraft 

  • 0 in reply to Chris Kraft
    Prodigy 140 points

    I have a similar situation to Q2.

    I have an application whereby I need to clone the EDID of a VGA monitor. plus do some level translation. Best I have found so far is using two TCA9517's.. The first is used simply at VCCA = VCCB buffer between the common EDID bus and the EEPROM, in order to gate/remove the EEPROM from the common I2C bus.. (I2C EEPROM is on the B side, Common Bus on the A side)

    Here is where it gets tricky.. VCCA s/b <= VCCB.. So B is on the +5 Common EDID side of the world and my VCCA +3.3V side points to my processor. Happy joy and translation correct.. But I want my processor to be able to use the EN pin to assert on the EDID bus, but it lives on the B-Side.. EN Vih is VCCB * .7 and +3.3 will not make it. I would prefer not to have to use an additional level shifter..

    Suggestions?