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Configuration of PCI Bridge 2050B

DEEPAK GUPTA3
Prodigy 30 points

Hello,

I'm developing a board and I'm using the PCI2050B bridge connected to a FPGA V-6 as target and configuring the PCI Bridge through Power PC. PCI bridge is running in 33 MHz configuration both primary and secondary side.  While communication with V-6 FPGA, when ever data is captured in Chip Scope it is not coming as as per spec, First address is coming,after that in place of valid data some junk type of address is coming after that  only data is coming. Where as per spec after address valid data should appear.

For your reference snap shot of chip scope is attached

1157.New Microsoft Office Word Document.doc

Deepak

  • 0
    TI__Guru* 76130 points

    Hello Deepak,

    Is the attached capture a read, configuration or write transaction?

    Can you take a scope capture showing the following signals: CLK, FRAME#, AD, C/BE#, IRDY#, TRDY#, DEVSEL, REQ#, GNT#.

    Can you send your schematic?

    What is the operating system?

    Is this a random failure? Are you able to communicate with the FPGA sometimes?

    Does a power cycle fix the issue?

    I am wondering of a possible type 0/1 transaction issue or an interrupt mapping issue.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 30 points

    Hi,

    Thanks for your response.

    This captured data is memory write cycle. I am using Power PC running  on INTEGRITY OS. As we can see in captured data

    that C/BE_2 is not getting 0 when C/BE_0 and C/BE_1 are getting 0. which will arise the reserved condition and

    that time this junk 32 bit data is coming. Further I am sending the schematic of PCI Bridge. Primary side it is connected withMPC8548 Power PC and secondary side on V-6 FPGA.

    is there issue due to length of the signal, because PCI bridge and FPGA both are in different Board?

    I am facing this issue consistently not able to communicate with FPGA.

    6378.New Microsoft Office Word Document.docx

  • 0 in reply to DEEPAK GUPTA3
    Prodigy 30 points

    Hi,

    Continuing with same problem, here I am giving more data to get the solution for the problem of configuring the PCI Bridge 2050B.

    5353.Presentation1.pptx

  • 0 in reply to DEEPAK GUPTA3
    TI__Guru* 76130 points

    Hello,

    I am sorry this is taken so long, I haven't been able to reproduce the issue with our EVM.

    Are you using a voltage level translator?

    Are you able to take a logic capture of the primary side of the bridge?

    Is ti possible to disconnect the FPGA that is sharing the primary bus with the bridge?

    The bus capture on the document attached show TRDY# always asserted? or you have the logic capture inverted? 

    It seems also that after FRAME# is asserted the AD lines remain the same for over 5 clock cycles, the Address phase should be completed in the first clock cycle. Or maybe this is also only a capture artifact...?

    Is IRDY# inverted on the capture?

    Regards.