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DS90UB925Q I2S Timing Requirements

Daisuke Maeda
Guru 20035 points
Other Parts Discussed in Thread: DS90UB927Q

When are the input audio samples that received at the I2S pins captured?

In the datasheet the setup and hold times to/from PCLK for the data input including the I2S pins (I2S_CLK, I2S_WC, I2S_DA) are defined. Does this mean that the input audio samples are captured on the edge of the PCLK?

Our customer is concerned that the input audio samples which are not synchronized to PCLK cannot be captured correctly.

Best regards,

Daisuke

 

  • 0
    Guru 20035 points

    Hi,

    I understand that the I2S_CLK frequency below PCLK/4 or 12.288MHz, whichever is lower, is allowed.

    e2e.ti.com/.../362825

    The FPD-Link III application note (SNLA221) describes the transport methods. Each of the serializer and the deserializer has the I2S audio samples buffer and the deserializer has the I2S PLL that recovers the I2S clock. It seems that the input audio samples that received at the I2S pins can be captured without using the PCLK.

    In the datasheet the setup and hold times to/from PCLK for the I2S pins (I2S_CLK, I2S_WC, I2S_DA) are defined. Is this a typo?

     

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Guru 20035 points

    Hi,

    The DS90UB927Q datasheet defines an I2S_CLK pulse duration as follows:

    "I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK periods to verify sampling and supersedes the 0.35*TI2S_CLK requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK"

    I guess that if the DS90UB925Q and the DS90UB927Q are about the same I2S receiver specifications an I2S_CLK pulse duration must be longer than "2 PCLK periods + 2.0nsec" because for the data input the setup time to PCLK or the hold time from PCLK must not be shorter than 2.0nsec.

    Is my guess correct?

    Best regards,

    Daisuke