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SN65LVCP114 SFI interface experiencing CRC

Ky Le
Prodigy 130 points
Other Parts Discussed in Thread: SN65LVCP114

We are bringing up boards which use 2 TI SN65LVCP114.  

Issue:  Packets drop and CRC errors between Line side SFP+ pairs.

Solution:  Adjust VOD to 600mV and shutdown port B’s lanes (Pink Path in diagram) help reducing the issue.  We still see a few errors but no packet drop.

Question:

1.  Do you have any suggestion on what we should try to configure the SN65LVCP114?  

2.  Please confirm the register settings of 0x04, 0x08, 0x0C in data sheet are correct

3.  If you would like to see any register settings of the SN65LVCP114 devices, please let us know.

  • 0
    TI__Expert 5455 points
    Hello Ky Le

    Sorry for my late reply.
    Can you tell me the configuration of these registers? How long is your tracer or What is your loss in it? and Can you send me your configuration of the registers 0x03, 0x07 and 0x0B?

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points

    Hi Francisco,

    We use 2 SN65LVCP144 and both devices' settings are the same.

    -  Register 0x03 = 0x00

    -  Register 0x07 = 0x00

    -  Register 0x0B = 0x00

    The trace lengths average for Lane 0 are:

    -  SFP+ RX #1 ---> SN65LCP144 #1 (Cin) = 3.104 inches.  

    -  SN65LCP144 #1 (Aout) --->  SN65LCP144 #2 (Ain) = 3.417 inches.

    -  SN65LCP144 #2 (Cout) ---> SFP+ TX #2 = 3.104 inches

    Total data path length 9.625 inches.

    Thank you for your help.

  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    We don't have this device, I guess you want to talking about of SN65LVCP114, if that is true, please

    Can you try to change the Gain factor to .5? and

    Can you send me your current configuration of the registers 0x04, 0x08 and 0x0C?

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points

    Hi Francisco,

    Sorry for the typo.  Yes, the device we are using is SN65LVCP114.

    Yes, we tried to reduce the gain factor to .5.  This reduce the error rate but there are still errors.

    Register 0x04 = 0x00

    Register 0x08 = 0x00

    Register 0x0C = 0x00

    Did you review my trace lengths and have any feedbacks?

    Thank you,

  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    Why do you use 2 lvcp? Your length is short and I think you can do it with one lvcp. It could be better if you put the lvcp in the middle for the connection. Sorry for this late observation.

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points
    Hi Francisco,

    Our application requires to be in a mode where we use the lvcp to loop from one port to another. We have 4 pairs of ports so we use 2 lvcp.

    You mentioned our length is short. What is the minimum length requirement for the lvcp?

    Thanks,
  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    This lvcp has since 1.3 dB to 13.9 dB of gain . With the lower gain you can have short length, but I think may be you could need to connect a long channel, then I think you can have just one lvcp. Do you consider the main characteristic of this lvcp (decision feedback equalizer (DFE) technology)? If is possible, Can you send me a block diagram of your connection?

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points
    Hi Francisco,

    I have the lvcp's eq settings to the lowest 1.3dB.

    I am not sure if we need the DFE. Maybe you can explain a little bit regarding this technology. Are you saying for shorter distances, we do not need DFE? Is there a way to turn it off?

    I can send you the block diagram, however, I am having problem attaching the file into this forum.
    Can we do this via email?

    Thanks,
  • 0 in reply to Ky Le
    Prodigy 130 points

    Hi Francisco,

    I tried to attached the block diagrams here.  Let me know if you can see them.

    Regards,

    Document1.docxHoward project TI SN65LVCP114.pdf

    ixia lcvp.tiff

  • 0 in reply to Ky Le
    TI__Expert 5455 points

    Hello Ky Le

    The DFE technology is about of the possibility to choose the input A or/and B and have the output on C port (mux) and vise versa (demux). You can see easier this like a switch. Now I can see the pink path with your diagram (:p). I guess you need to send a signal from FPGA to SFP and receive the feedback. I recommend to use just one channel (channel A) with your current configuration on the register 0x01 (I think is 00) like the figure.  Please make this change and send me your feedback

    Best regards 

    Francisco Zamudio

  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points
    Hi Francisco,

    In our application, we have 2 modes:
    - Mode 1: Registers 0x00 of both lvcp are 0x00. In this mode, we are required to have the blue/blac paths (A channels of the lvcp). The SFPs pairs will communicate with each others and NOT the FPGA.
    - Mode 2: Registers 0x00 of both lvcp are 0x0F. In this mode, we are required to have the FPGA communicate with each SFP separately (Same as your diagram).

    Our issue is we are observing CRC's in both modes. If the traces are too short, do you have any suggestion?

    Not sure what changes you are requesting and waiting for feedbacks. Your suggested diagram is our mode 2.

    Thank you,
  • 0 in reply to Francisco Javier Zamudio
    TI__Expert 5455 points

    If you need to attach something, choose the option "use rich formatting", with it you'll have more options.

    Regards

  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points
    Thanks, I got it working yesterday.
  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    I think you didn't know how to work this lvcp and I didn't to understand your app but now is more clear. The correct register of the configuration of this lvcp is 0x01, 0x00 is for configuration of the communication mode ("Switching logic is controlled by GPIO or I2C" ) and power operation (Power down the device) please confirm if you change the register 0x01.

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points

    Hi Francisco,

    Yes, we changes Register 0x01 between values 0x0F and 0x00 to switch our mode.

    Attached is the diagram with the EQ's, Gain's, and VOD settings which helps eliminate the CRCs.

    Please review and provide feedback if you see any issues.  

    Thanks,

    Windows 7 x64 Edition printed document.pdf

  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    Please Can you send me an eye diagram of your test in both modes?

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points

    Hi Francisco,

    We do not have a network analyzer in our lab to measure the eye diagram.

    Does Ti have a local lab in Northern California where you can help us arrange for us to measure the eye diagram?

    Thanks,

  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    With your information, I think it could be better if you use 1.3 dB, gain=.5 and VOD=600 mV, Do you know what is your loss? I would like to have an answer with the mode 2 first and latter the other mode. In your diagram the SPF TX and RX are swap, please Can you verify that (is for the direction of your arrows)? I'd like if is possible check your connection and the caps in the correct place, also please check your tracers (it could be better if you know your loss).
    Currently I'm not in this place, I hope to help you for this field, but try to be more clear with your information please.

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points
    Hi Francisco,

    We are trying to get the eye-diagram tools to get them measure. Once I have them, I will send it to you.

    The SFP's module TX and RX are from the module to the line side convention. So they are OK.

    I do have 1 question:
    - When we put any of the port of the lvcp114 in loop back mode, do the EQ, VOD and Gain settings has any affect?

    Thanks,
  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    Excellent! Then our problem is just the mode 1 right? and yes, these factors can change in this mode, if is possible please test with this mode and send me your feed back.

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points

    Hi Francisco,

    Yes, for mode 2 we can use our FPGA to look at the eye-diagram.  For mode 1, we will need an external analyzer to measure the eye-diagram which I do not have right now.

    Can you please confirm on my previous question regarding the loop back mode?  Especially on port C of the LVCP because I can change registers setting for VOD, EQ and Gain but I have no way view the eye on the C ports.

    In addition, please confirm the settings for registers 0x04, 0x08, 0x0C in the data sheet are correct.  We are questioning why the settings have many repeated values.

    Thanks,

  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le
    Currently I check it out with other group and I wait it the correct function of the registers. Please wait me with this question, I think it need to be OK because these registers are a main part of this lvcp.
    On the other hand, please try to have a right function with one mode and send me a detailed feedback.
    Please confirm
    - Don't you have an eye diagram yet?
    - Do you have a right connection in the lvcp (connectors, cables, capacitors)? Please check it out again.
    - Please test again with the loop back mode and send me your feedback

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    TI__Expert 5455 points
    Hello Ky Le

    I have the answer by the team and they say yes, is possible to change these settings in loop back mode. Please check the communication link and the procedure to work with I2C. How to know that it have a bad answer? Do you have some information about your answer by the device?

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    TI__Expert 5455 points
    Hello Ky Le

    I confirm the registers with the team and these are OK. Please I need more information about your issue and some measure that confirm your problem.

    Best regards
    Francisco Zamudio
  • 0 in reply to Francisco Javier Zamudio
    Prodigy 130 points

    Hi Francisco,

    We have confirmed the registers settings and the data path are correct.  We are still trying to get the equipments to get the eye diagrams.

    However, I was browsing Ti's forum and ran across the topic SN65lvcp114 SFI interface.  Michael Peffers mentioned for SFI links, it is recommended that we have some ISI before reaching the equalizer of the lvcp114 or there might be some over equalization.  I think this is the problem we are seeing.

    Do TI have a recommended trace length between SFP+ modules and the SN65lvcp114.  How about the length between 2 lvcp114?

    Thanks,

  • 0 in reply to Ky Le
    TI__Expert 5455 points
    Hello Ky Le

    This is possible but it could be better if you have some measure about your issue and if is possible send me your information. I understand that, the frequency is really high and the signal is very sensitive, but I need to know How do you have your results in your test?

    Best regards
    Francisco Zamudio