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TLK10232 read MDIO issue

Other Parts Discussed in Thread: TLK10232

Hi Sir:

Environment setting as follows.
The external OSC is 156.25MHz for 10G-KR.
The SFP+ Copper connect to 10G switch.
The other switch doesn't display link up function.

Could you provide solution or PHY initial code to me how to debug?

 

1E.000F

[3] RX_LS_OK

[2] TX_LS_OK

[1] LS_PLL_LOCK

[0] HS_PLL_LOCK

 

MDIO#1 PHY=0, DEV=0x1e(30), REG=0x000f(15): 0x191b

MDIO#1 PHY=0, DEV=0x1e(30), REG=0x000f(15): 0x191b

 

We try to enable PCS loopback (03.0014), and disable AN (07.0000) and LT (01.0096).
The channel status 1E.000F[3:0] is still 0x3. i.e. still not link up.

 

Thank you for your support.

  • following hugo's post, is there any demo code in TLK10232 for customer reference?
  • Now we can read out the value of 1E.000F as 0x5c03, and ping out ok. Why are the bits [3:2] not ok ?
  • Hi Hugo,

    For XAUI-to-SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 auto-negotiation and 10G link training. To do this, follow this procedure:

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)

    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).

    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12

    4. Disable link training by writing 16’h0000 to 0x01.0096

    5. Write 16’h03FF to 0x1E.8020.  This allows the link settings that would normally be configured through KR training to be configured manually instead.

    6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004.  For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.  This can be a starting point, but you may need to do some BER testing to optimize the values. As you know every system is different, hence, user needs to perform a "tuning" of the device (Equalization).

    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

    At this point the device should be properly configured. Please let us know if you need any more help.

    I hope this helps.

    Best Regards!

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • Hi, Luis Omar Morán Serna

    After your instruction, we still get a value of 0x5c03 on 1E.000F.

    Do we need to fine tune the 1E.0003 and 1E.0004 to get the 1E.000F[3:2] to true?

    At the present, we can transfer file using FTP protocol.

  • Hi Chiu,

    Several registers need to be configured according to the system requirements. Hence, you will need to perform a tuning of TLK10232 to get the best configuration of the device.

    Attached you will find a guideline for the tuning of the device.

    Best Regards!

    LuisTLK10034_link_training_app_note (1).doc

  • Dear Luis,

    We get a value of 0x5c03 on 1E.000F. It is correct or not ?

    The bits [3] and [2] on 1E.000F is not OK.

    BRs,

    Chialang.

  • Hi Chialang,

    Value 0x5C03 on 1E.000F (Channel_Status_1) is OK, bit [3] and bit [2]. Both bits are valid just in 10G mode (General Purpose). As you know TLK10232 has 3 modes: 10GBASE-KR, 10G General Purpose and 1GBASE-KX.

    Regards!
    Luis Omar Morán Serna
    High Speed Interface
    SWAT Team