DS32EL0124's register setting

Hi Nao,

It is preferable that you generate and check for errors within your FPGA for ease of use, as BIST mode may be more complex to set up.

For the bit error detection, the DS32EL0421/DS32EL0124 are capable of performing an internal bit error self test (BIST). This only checks for errors between the DS32EL0421 output and the DS32EL0124 input. It does not take into account the parallel LVDS data integrity of either device. Note that the BIST operation disrupts the normal operation of the devices. When in BIST mode, the DS32EL0421 ignores any data present on the parallel LVDS inputs and instead generates its own PRBS sequence.

I can send you instructions for operating this test mode, but again, the best way to measure link performance and reliability is to generate and check for errors within the FPGAs.

Michael

Hi, Michael-san

Thank you for your quick reply.
I understand about BIST mode of DS32EL0421/DS32EL0124.

Could you please send me instructions or documents for operating this test mode(BIST)?

Regards,
Nao