Hi,
We use TLK10232 chip in the following configuration:
(1) LS_side
Xilinx FPGA (XAUI 3.125MHz 4lane) => TLK10232
(2) HS_side
TLK10232 (1lane 10G-KR) => opt.SFP module => optic Cable => opt.SFP module => TLK10232 (1lane 10G-KR)
When our PCBs operate with this particular chip, we faced the following problem: after initialization and reaching normal operative mode at indoor temperature, the line is stable and no errors appear.
Then, when the environment temperature cools down, errors emerge in the line.
We conducted research and noticed the following:
1. First, capturing of AGC disappears, the bit of HS_AGC_LOCKED registry, 0x1E:0x000F sets to “0. By the temperature goes down we notice that errors emerge in the line, but they are corrected: FEC corrected blocks=4. When further temperature decrease, uncorrected errors appear: FEC Uncorrected blocks=7.
At the same time, there aren’t errors on LS:
LN0_ERROR=0
LN1_ERROR=0
LN2_ERROR=0
LN3_ERROR=0
When the temperature grows, line operability restores.
Then we conducted another test: we cooled only TLK10232 (locally on one of the boards) and errors appeared again on that circuit board where TLK10232 was cooled down.
When we turn on and initialize boards at reduced temperature, errors appear immediately, AGC capturing does not occur.
Our opinion is that the problem is related to the reception path and possibly to a large signal level from the SFP module (using Finisar Corporation FTLX2071D3xx modules). Length of traces from TLK10232 to SFP module is less than 15mm .
For optimizing and settings the channel we used information from the following link:
e2e.ti.com/.../1645058
e2e.ti.com/.../457047
We also used the following datasheets:
tlk10232.pdf
slla351.pdf
tlk10232_BringupProcedures_v2.pdf
4520.TLK10034_link_training_app_note (10).doc
Annex 1.
Our optimal setting and initialization of TLK10232:
Write_dev_1E_mdio(0x0, 0x8610);// reset
Write_dev_1E_mdio(0x0, 0xe10);// reset
Write_dev_07_mdio(0x0, 0x2000); //AN_CONTROL OFF
Write_dev_01_mdio(0x96, 0x0); // TRAINING_ENABLE_OFF
Write_dev_1E_mdio(0xE, 0x8); // Channel datapath reset control
Write_dev_01_mdio(0x9000, 0x24d);
Write_dev_1E_mdio(0x8101, 0x4);
Write_dev_1E_mdio(0x8100, 0x4);
Write_dev_1E_mdio(0x8100, 0x0);
Write_dev_01_mdio(0x9001, 0x200);
Write_dev_01_mdio(0x96, 0x2); // TRAINING_ENABLE_ON
Write_dev_01_mdio(0x9005, 0x1C00);// packet
Write_dev_01_mdio(0x9002, 0x0);// Disable a 500ms time-out-counter
Write_dev_01_mdio(0x9003, 0x0);// Disable a 500ms time-out-counter
Write_dev_1E_mdio(0x1, 0xB00);// CHANNEL_CONTROL_1
Write_dev_1E_mdio(0x2, 0x831c);// HS_SERDES_CONTROL_1
Write_dev_1E_mdio(0x3, 0x88c8);// 15..12 HS_SWING[3:0] TYPICAL AMPLITUDE (mVdfpp) 800, the attenuator on
Write_dev_1E_mdio(0x4, 0xd500);// 14..12 HS_EQPRE[2:0], HS_TWCRF[4:0] Cursor Reduction Factor (Default 5’b00000). bit 15 Activating this parameter adds intersymbol interference (ISI)
Write_dev_1E_mdio(0x5, 0x3088);// 12..8 HS_TWPOST1[4:0], 7..4 HS_TWPRE[3:0], 3..0 HS_TWPOST2[3:0]
Write_dev_1E_mdio(0x7, 0xfc04); //LS set acc eq
Write_dev_1E_mdio(0x9, 0x33f); //HS -> status LOS LED
Write_dev_1E_mdio(0xA, 0x5FFF); //LS -> status LOS LED, Set
Write_dev_01_mdio(0x8001, 0x9c1c); // set fifo rx tx 12 deep
Write_dev_01_mdio(0xab, 0x3); // en FEC
Write_dev_1E_mdio(0xE, 0x8); // Channel datapath reset control
Annex 2 - Registers after initialization:
Read_dev_1E_mdio(0x8031)=0x3088;
Read_dev_1E_mdio(0x8032)=0xc08;
Annex 3 - Settings after initialization:
Write 1’b1 to 0x01.9001 bit 12
read register 0x01.9022 (16 times)
TEST_BER_0=FFFF
TEST_BER_1=FFFB
TEST_BER_2=FFF9
TEST_BER_3=FFFF
TEST_BER_4=FFFF
TEST_BER_5=FFFF
TEST_BER_6=FFFF
TEST_BER_7=FFFF
TEST_BER_8=FFFF
TEST_BER_9=FFFF
TEST_BER_10=FFFF
TEST_BER_11=FFFF
TEST_BER_12=FFFF
TEST_BER_13=FFFF
TEST_BER_14=FFFF
TEST_BER_15=FFFF
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Hi,
We use TLK10232 chip in the following configuration:
(1) LS_side
Xilinx FPGA (XAUI 3.125MHz 4lane) => TLK10232
(2) HS_side
TLK10232 (1lane 10G-KR) => opt.SFP module => optic Cable => opt.SFP module => TLK10232 (1lane 10G-KR)
When our PCBs operate with this particular chip, we faced the following problem: after initialization and reaching normal operative mode at indoor temperature, the line is stable and no errors appear.
Then, when the environment temperature cools down, errors emerge in the line.
We conducted research and noticed the following:
1. First, capturing of AGC disappears, the bit of HS_AGC_LOCKED registry, 0x1E:0x000F sets to “0. By the temperature goes down we notice that errors emerge in the line, but they are corrected: FEC corrected blocks=4. When further temperature decrease, uncorrected errors appear: FEC Uncorrected blocks=7.
At the same time, there aren’t errors on LS:
LN0_ERROR=0
LN1_ERROR=0
LN2_ERROR=0
LN3_ERROR=0
When the temperature grows, line operability restores.
Then we conducted another test: we cooled only TLK10232 (locally on one of the boards) and errors appeared again on that circuit board where TLK10232 was cooled down.
When we turn on and initialize boards at reduced temperature, errors appear immediately, AGC capturing does not occur.
Our opinion is that the problem is related to the reception path and possibly to a large signal level from the SFP module (using Finisar Corporation FTLX2071D3xx modules). Length of traces from TLK10232 to SFP module is less than 15mm .
For optimizing and settings the channel we used information from the following link:
We also used the following datasheets:
tlk10232.pdf
slla351.pdf
tlk10232_BringupProcedures_v2.pdf
4520.TLK10034_link_training_app_note (10).doc
Annex 1.
Our optimal setting and initialization of TLK10232:
Write_dev_1E_mdio(0x0, 0x8610);// reset
Write_dev_1E_mdio(0x0, 0xe10);// reset
Write_dev_07_mdio(0x0, 0x2000); //AN_CONTROL OFF
Write_dev_01_mdio(0x96, 0x0); // TRAINING_ENABLE_OFF
Write_dev_1E_mdio(0xE, 0x8); // Channel datapath reset control
Write_dev_01_mdio(0x9000, 0x24d);
Write_dev_1E_mdio(0x8101, 0x4);
Write_dev_1E_mdio(0x8100, 0x4);
Write_dev_1E_mdio(0x8100, 0x0);
Write_dev_01_mdio(0x9001, 0x200);
Write_dev_01_mdio(0x96, 0x2); // TRAINING_ENABLE_ON
Write_dev_01_mdio(0x9005, 0x1C00);// packet
Write_dev_01_mdio(0x9002, 0x0);// Disable a 500ms time-out-counter
Write_dev_01_mdio(0x9003, 0x0);// Disable a 500ms time-out-counter
Write_dev_1E_mdio(0x1, 0xB00);// CHANNEL_CONTROL_1
Write_dev_1E_mdio(0x2, 0x831c);// HS_SERDES_CONTROL_1
Write_dev_1E_mdio(0x3, 0x88c8);// 15..12 HS_SWING[3:0] TYPICAL AMPLITUDE (mVdfpp) 800, the attenuator on
Write_dev_1E_mdio(0x4, 0xd500);// 14..12 HS_EQPRE[2:0], HS_TWCRF[4:0] Cursor Reduction Factor (Default 5’b00000). bit 15 Activating this parameter adds intersymbol interference (ISI)
Write_dev_1E_mdio(0x5, 0x3088);// 12..8 HS_TWPOST1[4:0], 7..4 HS_TWPRE[3:0], 3..0 HS_TWPOST2[3:0]
Write_dev_1E_mdio(0x7, 0xfc04); //LS set acc eq
Write_dev_1E_mdio(0x9, 0x33f); //HS -> status LOS LED
Write_dev_1E_mdio(0xA, 0x5FFF); //LS -> status LOS LED, Set
Write_dev_01_mdio(0x8001, 0x9c1c); // set fifo rx tx 12 deep
Write_dev_01_mdio(0xab, 0x3); // en FEC
Write_dev_1E_mdio(0xE, 0x8); // Channel datapath reset control
Annex 2 - Registers after initialization:
Read_dev_1E_mdio(0x8031)=0x3088;
Read_dev_1E_mdio(0x8032)=0xc08;
Annex 3 - Settings after initialization:
Write 1’b1 to 0x01.9001 bit 12
read register 0x01.9022 (16 times)
TEST_BER_0=FFFF
TEST_BER_1=FFFB
TEST_BER_2=FFF9
TEST_BER_3=FFFF
TEST_BER_4=FFFF
TEST_BER_5=FFFF
TEST_BER_6=FFFF
TEST_BER_7=FFFF
TEST_BER_8=FFFF
TEST_BER_9=FFFF
TEST_BER_10=FFFF
TEST_BER_11=FFFF
TEST_BER_12=FFFF
TEST_BER_13=FFFF
TEST_BER_14=FFFF
TEST_BER_15=FFFF
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