SN75DP130 eye opening issue

Kazuhiko Hirano

Genius 15838 points

Other Parts Discussed in Thread: SN75DP130

Hellow,

We are evaluating SN75DP130 right now, but we can not get good eye opening.

We can not sometimes get enough high level amplitude like the waveform enclosed by red line box below.

cid:image002.jpg@01D1DDEB.A31A7C10

Any suggestions or advices to fix this issue and improve the eye opening?

For your reference, our register setting for EQ is as follows.

EQ_I2C_ENABLE = 1

AEQ_L0_LANE0_SET = 0

AEQ_L1_LANE0_SET = 0

AEQ_L2_LANE0_SET = 0

AEQ_L3_LANE0_SET = 0

Best regards,

K.Hirano

over 9 years ago

0 Kazuhiko Hirano over 9 years ago

TI__Genius 15838 points

cid:image002.jpg@01D1DDEB.A31A7C10

0 Moises Garcia over 9 years ago

TI__Mastermind 23815 points

Hi Kazuhiko,

Could you provide more information about your application?

Is this a source or sink application?

Can you provide schematic and layout?

I see you are configuring DP130 via I2C, you could provide the registers being written and the values?

Are you using link training?

What data rate is showing this behavior?

You can send me an email with files.

Regards

0 Kazuhiko Hirano over 9 years ago

TI__Genius 15838 points

Eye diagram.pptx

0 Moises Garcia over 9 years ago in reply to Kazuhiko Hirano

TI__Mastermind 23815 points

Hi Kazuhiko,

In the image you uploaded there is a lot of noise in the signal, could you provide schematic, layout and available test reports, have they run EMI and crosstalk tests?

Regards

0 Kazuhiko Hirano over 9 years ago in reply to Moises Garcia

TI__Genius 15838 points

Hello,

It is sink application.

But, my customer can not publish their schematics and layout since they are proprietary information.

Anyway, let me ask one more question.

SN75DP130 is used between two FPGAs.

The two FPGAs do the link training each other.

During the link training between the two FPGAs what should SN75DP130 do?

LINK_TRAINING_ENABLE should be “0” or “1”?

Best regards,

K.Hirano

0 Moises Garcia over 9 years ago in reply to Kazuhiko Hirano

TI__Mastermind 23815 points

Hi Kazuhiko,

If this a sink application DP130 we strongly recommend to configure it by I2C. http://www.ti.com/lit/an/slla349/slla349.pdf

You have to disable link training, by writing a zero to bit 2 of register 04h.

The image you shared seems to have a lot of noise, that's why I wanted to review their layout, there are other signals close to DP lanes?

We can't do much if there is no schematic, layout, tests reports to review.

Regards

Interface

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SN75DP130 eye opening issue