TUSB7320: power on reset implementation

Daisuke Maeda

Guru 20295 points

Part Number: TUSB7320

Is there the timing relationship between PERST# and GRST# resets?

Can PERST# and GRST# be tied and driven together?

Best regards,

Daisuke

over 9 years ago

0 Daisuke Maeda over 9 years ago

Guru 20295 points

Hi,

I found this answer here: e2e.ti.com/.../507516

PERST# and GRST# can be tied and driven together.

Please correct it if my understanding is not correct.

Best regards,

Daisuke

0 Gerardo over 9 years ago in reply to Daisuke Maeda

TI__Genius 11280 points

Hi Daisuke,

That's correct but the power-up requirements must be followed. I'm talking about PERST can be deasserted until a minimum of 100 μs after applying a stable PCI Express reference clock and a minimum of 100 ms after applying power.

Regards,

Gerardo

0 Daisuke Maeda over 9 years ago in reply to Gerardo

Guru 20295 points

Hi Gerardo-san,

Thank you for your reply.

Best regards,

Daisuke

Interface

Interface forum

TUSB7320: power on reset implementation