SN65DSI86: Asking for the SN65DSI86ZQER eDP resolution support

Hello SHH,

In all applications, the eDP output rate must be less than or equal to the DSI input rate. If the DSI86 supports an input resolution of 2160x1440 using only 4 data lanes will depend on the DSI Clock rate. For example: 

Stream Bit Rate = PixelClock × bpp

1. 

Stream Bit Rate = 186.62 (approx) × 24

Min Required DSI Clock Frequency = StreamBitRate /

(Number_DSI_Lanes × 2)

Min Required DSI Clock Frequency = 4.47/ (4 × 2)

Min Required DSI Clock Frequency = 560MHz

2. 

Stream Bit Rate = 186.62 Mhz × 18

Min Required DSI Clock Frequency = StreamBitRate /

(Number_DSI_Lanes × 2)

Min Required DSI Clock Frequency = 3.35/ (4 × 2)

Min Required DSI Clock Frequency = 420MHz 

Regards