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Hi,
Our use case is to convert video of resolution 1920x1080 (@60 fps) from Single DSI to Dual LVDS. We are seeing that using SN65DSI85 is incompatible with our LED Input format requirement.
Below is the Comparison we have done,
We are comparing our output data format of SN65DSI85 with our LED supported LVDS input. While observing data format, We have found that Dual-Link LVDS output is not compatible with the LED's input we have chosen.
Below Image 1 shows LED's Input Data & Image 2 shows SN65DSI85 chips's Dual-Link Output Data.
Image 1 : LED Input Data Format
Image 2 : SN65DSI85 Dual Link Output Data
From the above Images What we have concluded is
1. In LED Input data at A_Y0P/N, Green component has pixel number 0 with Bit 2
2. In SN65DSI85 Output data, at A_Y0P/N, Green component has pixel odd with Bit 0
3. In LED Inout data, at A_Y1P/N, Green Component with Pixel 0 and bit sequence is 7,6,5,4,3
4. In SN65DSI85 Output data, at A_Y1P/N, Green Component with Odd Pixel and bit sequence is 5,4,3,2,1
From the above comparison it seems that using SN65DSI85 is incompatible with our LED Display.
We have few doubt from the above comparison,
1. Is our understanding correct, If not then please help me to get it clear ?
2. Is there any such configuration in SN65DSI85 which allow us to change the Pixel value and it's bits values to match with our LED input requirement ? (As from SN65DSI85 Datasheet, It is written that Dual-Link LVDS has Odd pixels for Channel A and Even Pixels for channel b on Page 16 & 17)
3. If SN65DSI85 will not support such configuration then, Is there any other Part which is best fit for the requirement ?
Thanks & Regards,
Pratik
Hi Joel,
Thanks for your reply. Can you advice if the same register configuration (to support dual mode using format 1) is possible with SN65DSI84 chip as well?
Regards
Kinjan
Hello Joel,
As suggested by You, I have generated DSI file using DSI Tuner. I have attached DSI file and Screenshots of inputs feed to the DSI Tuner application.
We are using these parameters for our OLED Display with resolution of 1920x1080 @60 fps at 74.25 Mhz LVDS input clock.
Please have a look to this file and give us your valuable input.
Thanks & Regards,
Pratik Panchal
Hello Pratik,
In case of dual LVDS operation the LVDS_HActive field should be half of the total number of pixels (960).
Regards
Hello Joel,
Thanks for your suggestion. I have updated all parameters in the DSI Tuner as per our requirement.
Please have a look in to it and give your suggestions, Is it fine or anything is wrong?
Thanks & Regards,
Pratik Panchal
Hello Joel,
Thanks for reviewing this.
Just for clarification, Internal pattern means Test Pattern in DSI Tuner?
Regards,
Pratik