• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 2301 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLK10232: Unexpected Link down at XAUI side

Takashi Onawa
Genius 13200 points
Part Number: TLK10232

Hi Team,

My customer is facing the issue that FPGA is stuck sometime when issuing Data path reset on TLK10232. As far as we check the FPGA error status, it seems that FPGA gets Alignment error at XAUI line at the timing and can not sync again due to some reason. 

According to datasheet, TLK10232 automatically converts /A/, /K/ and /R/ character to Idle and outputs "Idle" pattern only(between data packet) on XAUI line continuously as default. We are guessing that this might be root cause of this issue.

Are there any registers to issue the characters for XAUI lane alignment?

The customer is using TLK10232 in 10G KR mode, so  FORCE_LM_REALIGN register change doesn't work because this register is only for 10G-KX mode. 

(I think that PCS_RX_DEC_CTRL_CHAR may be used, so please let me know if you know how this register behaves. )

 

Regards,

Takashi Onawa

  • 0
    TI__Genius 16150 points
    Hi Takashi,

    The customer has tried with PCS_RX_DEC_CTRL_CHAR to 1b'1 to pass these characters through as is RW?

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    TI__Genius 13200 points
    Hi Luis-san,

    Not yet. Can you test out what kind of difference will appear in the characters output from XAUI on your desk if possible?
    Also, I would like to know if there are any side effects by the change, prior to telling it to customer.

    Regards,
    Takashi Onawa
  • 0 in reply to Takashi Onawa
    TI__Genius 13200 points
    Hi Luis-san,

    Today, They tried PCS_RX_DEC_CTRL_CHAR to 1b'1 but It did not improve.

    Are there any findings on what kind of data is output when Datapath reset is done?

    Regards,
    Takashi Onawa
  • 0 in reply to Takashi Onawa
    TI__Genius 16150 points
    Hi Takashi-san,

    Could you provide the values of these registers please?

    CHANNEL_STATUS_1
    LS_STATUS_1

    Thanks,
    Luis
  • 0 in reply to Luis Omar Moran
    TI__Genius 13200 points

    Hi Luis-san,

    Here is the register values. I take 3 samples each OK and not sync condition. There are no big differences between the values and no strange points. As note, the switch pass is connected as below.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 16150 points

    What is the value of these registers:

    DST_CONTROL_1

    DST_CONTROL_2

    DSR_CONTROL_1

    DSR_CONTROL_2

    DATA_SWITCH_STATUS

    As well, what is the value of DST_PIN_SW_EN pin?

    I am asking this because it seems a data switch issue.

    Thanks,

    Luis

  • 0 in reply to Luis Omar Moran
    TI__Genius 13200 points

    Hi Luis-san,

    DST_PIN_SW_EN pin is not used.
    Here is the values which you requested.

    - ChA

    Switch control registers

    Changed only DST_CONTROL_1 as below
    DA:0x1E RA:0x0017 WriteData:0x2014
    Other SW settings as same as default

    DATA_SWITCH_STATUS

    The second read value is as following.
    4020h
    I see DST and DSR ON/OFF bit asserted in first read value after the data path reset.

    - ChB

    Switch control registers

    Changed only DSR_CONTROL_1 as below
    DA:0x1E RA:0x0019 WriteData:0x2518
    Other SW settings as same as default

    DATA_SWITCH_STATUS
    The second read value is as following.
    1080h
    I see DST and DSR ON/OFF bit asserted in first read value after the data path reset.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 16150 points

    Hi Takashi-san,

    According to the block diagram that you sent before, customer desires this data path:

    CHA

    LSINB ==> HSTXA

    CHB

    LSOUTB <==HSRXA

    Hence, they need to configure the data switch register as follows:

    CHA
    LSINB ==> HSTXA

    DST_CONTROL_1
    Write 0x2000
    MDIO control, DST_PIN_SW_EN = '0' (Default)

    DST_CONTROL_2
    Write 0x2C20 (Select alternate channel LS input)

    CHB
    LSOUTB<==HSRXA

    DSR_CONTROL_1

    Write 0x2500

    MDIO control, DST_PIN_SW_EN = '0' (Default)

    DSR_CONTROL_2
    Write 0xCC20 (Select alternate channel HS input)

     

    Please implement this configuration and let me know your results through the register DATA_SWITCH_STATUS. By the way, what is the current value of PRTAD0 pin?

    Thanks,

    Luis

  • 0 in reply to Luis Omar Moran
    TI__Genius 13200 points
    Hi Luis-san,

    Thanks for your suggestion.

    As I mentioned before, they got problem using the setting which you suggested and they applied force SW setting to avoid the issue.

    Eventually, The root cause of the FPGA stuck was that TLK10232's PLL was momentarily stopped during Datapath reset. So I recommend them to reset FPGA after the data path reest.

    In Last week, we reached out that conclusion and the issue was closed.

    Regards,
    Takashi Onawa