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XIO2001: System execute hibernate shutdown from WIN10

Part Number: XIO2001

Hi Sirs,

Sorry to bother you.

There is a problem feedback from our customer as below description, they use COMe module (skylake) and XIO2001 implement in their carrier board.

When the system execute hibernate shutdown from WIN10, the system will auto wakeup.

If we disabled PME SCI support on this PCIe port then the problem did not happen anymore (there are no any PCI device is plugged during test).

Suspecting the XIO2001 to set some of PME registers during shutdown process result in the system auto wakeup, do you have any suggestions for this problem or have you ever receive similar case from other accounts?

Also we found the problem happen on a particular condition…

The system shutdown from OS, then disconnect power:

àIf the VAUX does not fully discharge that still keep around 0.45V then power on again, the problem will happen on next shutdown.

àIf the VAUX has fully discharge to 0V, then the problem does not happen.

Could you help to check this problem?

Thanks!!

  • Hi,

    Please verify the following:
    PME# shall be connected to Vaux, otherwise it will trigger a wake signal every time power is removed.
    PERST# should not cause the WAKE# terminal to go low.
    WAKE# signal must have a system side pull-up.
    An incorrect power-up or power-down sequence could cause the bridge to erroneously assert WAKE#.

    PME# has hysteresis and so a pull-up is required. If PME# is not pulled up our device will pull WAKE signal low internally, especially when auxiliary power is enabled. If Vaux is supplied to the XIO2001, PME# must be pulled high to the Vaux rail and not to 3.3V. If PME# is pulled to 3.3V, when the system shuts down and the 3.3V rail is powered down, the XIO2001 will see the PME# line be pulled low, because the pull-up is now effectively a pull down, and immediately wake the system as it sees a wake event coming from a downstream device.

    Dennis
  • Hi Dennis,

    Thanks for your reply.

    The design of XIO2001 as below:

    1. PME# pull up to Vaux
    2. PERST# is come from chipset platform reset.
    3. Wake# pull up in system side.

     

    There are all follow design guide to design.

    We saw this problem happen if the system power on before Vaux/VDD_33_COMBIO fully discharge to 0V.

  • Hello,

    Please verify the customer is following the power-up and power-down sequence described in the XIO2001 datasheet, if they are not following them its posible to have unexpected behaviors.

    Regards,
    Roberto
  • Hi Sirs,
    As our customer’s feedback, the power up/down sequence are all meet spec requirement.
    The problem only happens if the system power on before Vaux/VDD_33_COMBIO fully discharge to 0V.
    Do you have any recommendation for this case?
  • Hello,

    Please double check that VDD_33_COMBIO layout implementation is following section "9.2.1.1.2 Combined Power Outputs" of XIO2001 Datasheet, if not this also can cause unexpected behavior this signal.

    Regards,
    Roberto
  • Hi Sirs,

    I have got the measured report for power sequence, it’s followed spec requirement. Could you help to double confirm? (attachment) ThanksS13009_XIO2001_PowerSupplySequenceWave_20170928_1.doc

  • Hello,

    The power sequence looks good, could you no please check they are following, VDD_33_COMBIO layout implementation is following section "9.2.1.1.2 Combined Power Outputs"?

    The recommended bypass capacitors for each combined output terminal are 1000 pF, 0.01 μF, and 1.0 μF.
    When placing these capacitors on the bottom side of the circuit board, the smallest capacitor is positioned next to
    the via associated with the combined output terminal and the largest capacitor is the most distant from the via.
    The circuit board trace width connecting the combined output terminal via to the capacitors must be at least 12 to
    15 mils wide with the trace length as short as possible.

    Other than the three recommended capacitors, no external components or devices may be attached to these
    combined output terminals.

    Regards,
    Roberto