Linux/DP83867IR: dp83867 output 125M clock

we have only one phy。

Hi Micheal,

The default value of bit [12:8] in register 0x170 is 0x0C which would output the 25MHz reference clock. When those bits are changed to 0x0B- 0x08 and 0x03-0x00, they will output 125MHz. Other bits of that register are dont care in this case and should be kept the same. I read 0x0C0E as default value on my setup and I keep the lower byte unchanged (0x0E) throughout the experiment.

-Regards,

Aniruddha 

Hi,

1. Can you read and share the register value of register 0x0170 after configuring [12:8] as 0x08.

2. Which pin you are measuring the clock out ?

3. Kindly share the schematics.

Regards,
Geet

LAN_DP83867IRR.pdf

I believe you are not commenting following in your program.

//val |= (0x4<<8);

Regards,
Geet

125M CLK is ok, but phy still can't work. (0x0170=0xe，Clock Output Select: Channel A receive clock)

 Is there any other suggestion? Thanks.

"125M CLK is ok, but phy still can't work. (0x0170=0xe，Clock Output Select: Channel A receive clock)"

You mean, you are able to see 125 MHz clock on CLK_OUT.

Can you please explain the problem you are facing now ?

now the 100M is ok,but 1000M is not ok.
[ 32.353548] stmmc_pltfr_fix_mac_speed: fix speed to 100
[ 32.353597] stmmc_pltfr_fix_mac_speed: fix speed for RGMII
[ 32.353621] ++++++SET_RGMII_100M+++++++
[ 32.353644] libphy: stmmac-0:00 - Link is Up - 100/Full
root@rsb4680:/ # ping 172.21.170.48
PING 172.21.170.48 (172.21.170.48) 56(84) bytes of data.
64 bytes from 172.21.170.48: icmp_seq=1 ttl=64 time=1.11 ms
64 bytes from 172.21.170.48: icmp_seq=2 ttl=64 time=0.506 ms
64 bytes from 172.21.170.48: icmp_seq=3 ttl=64 time=0.567 ms

[ 197.450854] stmmc_pltfr_fix_mac_speed: fix speed to 1000
[ 197.450902] stmmc_pltfr_fix_mac_speed: fix speed for RGMII
[ 197.450927] ++++++SET_RGMII_1000M+++++++
[ 197.450950] libphy: stmmac-0:00 - Link is Up - 1000/Full
1|root@rsb4680:/ # ping 192.168.1.1
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
From 192.168.1.2: icmp_seq=1 Destination Host Unreachable
From 192.168.1.2: icmp_seq=2 Destination Host Unreachable
From 192.168.1.2: icmp_seq=3 Destination Host Unreachable

and i enable the tx_clk/rx_clk delay ,my configurations as following:
val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
DP83867_DEVADDR, phydev->addr);
val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
DP83867_RGMII_RX_CLK_DELAY_EN);
phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
DP83867_DEVADDR, phydev->addr, val);

delay = (0x7 | (0x5<< DP83867_RGMII_TX_CLK_DELAY_SHIFT));
phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
DP83867_DEVADDR, phydev->addr, delay);

val = phy_read_mmd_indirect(phydev, 0x0170,
DP83867_DEVADDR, phydev->addr);
val &= ~(0x1f<<8);
phy_write_mmd_indirect(phydev, 0x0170,
DP83867_DEVADDR, phydev->addr, val);
val = phy_read_mmd_indirect(phydev, 0x0170,
DP83867_DEVADDR, phydev->addr);

our 1000M rgmii interface's waveform as bmp files

Hi,

Do you see issues on Rx or Tx path for ping ? Are you able to see your peer receiving the ping command ?

To configured the delay on RGMII interface, delay introduced by routing on Tx and RX paths has to be computed and additional delays can be introduced using the register 0x0086 as done above. Please refer to below Application Note on how to compute the delay numbers and compute 

Alternatively, you can try few numbers to see if you get the data going thru the interface ?

Regards,

Geet