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DP83867E: DP83867 - MDIO initialization

Aaron Spaete
Expert 4527 points
Part Number: DP83867E
Other Parts Discussed in Thread: DP83865

Team,

My customer has a DP83867 connected to a Xilinx Zynq Ultrascale+ SoC. We are using the MDIO Station Controller inside the processor section of the SoC and are getting inconsistency in talking via the MDIO. Sometimes it connects, and sometimes it does not.

 We found a link to a synchronization need between the Station Controller and the PHY looking at the DP83865 datasheet

https://e2e.ti.com/support/interface/ethernet/f/903/t/498858

I do not see anything in the DP83867 datasheet saying that this is also needed. Can you confirm whether or not the DP83867 requires the same synchronization initialization?

Regards,

Aaron

  • 0
    TI__Mastermind 19780 points

    Hi Aaron,

    The synchronization discussed in the DP83865 datasheet is a requirement for all SMI stations.  DP83867 also requires this 32 cycles of MDC, during which MDIO should be held high.

    The Reset timing and power-up timing diagrams of the DP83867 show the 32 MDC clocks needed while MDIO is pulled high.  MDC can clock more than 32 times if necessary as long as MDIO is held high.

    This is pretty standard for industry SMI controller design, and we have not had any problems with Zynq SoCs.  What is the erroneous behavior you are seeing?  Is the MDIO line being pulled to some mid-rail voltage?  Are the registers sending back incorrect values?

    Best Regards,