Dear:Sir
Now there are functional requirements to convert LVDS signals into SDI signals, and can you help recommend current mainstream chips
Thank you!!
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Dear:Sir
Now there are functional requirements to convert LVDS signals into SDI signals, and can you help recommend current mainstream chips
Thank you!!
Hi Havid,
I looked at the PPT, but it appears that there is no LVDS output from the CPU. Can you advise what data format for LVDS is being used? For example, is it OpenLDI or DDR?
Thanks,
Michael
Hi Michael
The LVDS data format as follow:
Comply with the TIA/EIA-644-A LVDS standard
Combine LVTTL IO, support LVDS/LVTTL data output
Support reference clock frequency range from 10Mhz to 148.5Mhz
Support LVDS RGB 30/24/18bits color data transfer
Support VESA/JEIDA LVDS data format transfer
Support LVDS single channel and double channel data transfer, every channel include 5 data lanes and 1 clock lane
If I want to use the LHM0040/LMH0340, Can help provide reference design(Including the schematic diagram and the PCB board layout) II can't find this information on the official websiteT
Thank you!!
Hi Havid,
If you wish to use the LMH0340, this will only enable you to use up to 3G-SDI for Full HD. From your block diagram, it appears that you are trying to design a 4K. Are you looking for something to serialize into 12G-SDI?
Regarding the LMH0340, note that the LVDS input is expected to be a 5-bit DDR signal that is typical from an FPGA:
Is this type of format and resolution compatible with what you are trying to accomplish?
Regards,
Michael
Dear:Michael
Thank you!!
I only use up to 3G-SDI for Full HD(1080P),So I will choose the LHM0340
Can help provide reference design(Including the schematic diagram and the PCB board layout)
I can't find this information on the official website
Thank you!!
SDV Serializer EVK Schematics Oct 23 07.pdfHi Havid,
Please attached note LMH0340 schematic.
Also, please note there needs to be FPGA to provide SMPTE 424 or other SMPTE protocol. Please below note a link to FPGA IP documentation that goes into further details on FPGA IP.
Regards,,nasser