This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
For our custom display solution, we are using the below serdes pair
Serializer : DS90UB921-Q1
Deserializer : DS90UH948-Q1
Display timings are configured properly in the kernel.
But we do not get anything up on the display.
serdes lock is established.
Serializer test patterns and deserializer test patterns also do not work with external clock timings.
Work-around:
If we run serializer pattern with internal clock, then we see that the pattern is coming on the display.
Later if we disable the pattern, then our HMI is up on the display.
Need support here to understand what configuration is set on serializer/de-serializer when we set the internal clock pattern ?
Note : we see only register 0x3B getting updated on deserializer side between working and non-working scenarios. This register has no mention in datasheet, seems to be reserved one.
Hello Pradeep,
Could you upload the register dumps (regular registers and the pattern generator indirect data registers) of the two cases:
1. the failed case that use external timing alone
2. the working case that first use internal timing and then disable the pattern.
By the way, what's the resolution, the frame rate and pixel frequency of your input signal?
Best regards,
Cera
Hi Cera,
I have attached file for register dumps (regular registers and the pattern generator indirect data registers) of the two cases.
1. the failed case that use external timing alone
2. the working case that first use internal timing and then disable the pattern.
Resolution : 800*480
Frame rate : 60
Pixel frequency : 2.54 MHz
================================================================================================================================================== NON-WORKING CASE - EXTERNAL TIMING ================================================================================================================================================== root@mmt:~# i2cdump -y -f 1 0x0C No size specified (using byte-data access) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: 18 00 00 ab 8a 00 78 00 00 00 00 00 05 00 00 00 ?..??.x.....?... 10: 00 00 0a 10 00 00 fe 5e a1 a5 00 00 00 00 00 00 ..??..?^??...... 20: 00 00 25 00 00 00 00 00 00 24 00 a0 00 00 00 00 ..%......$.?.... 30: 03 10 00 00 00 00 08 34 00 0a 20 21 00 00 f0 00 ??....?4.? !..?. 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 50: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ............... 60: 00 00 00 00 10 00 03 08 00 00 00 00 00 00 00 00 ....?.??........ 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ c0: 00 00 80 00 68 08 00 00 40 00 00 00 00 00 00 00 ..?.h?..@....... d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ f0: 5f 55 42 39 32 31 00 00 00 00 00 00 00 00 00 00 _UB921.......... root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x03 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x08 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x04 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x48 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x05 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x53 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x06 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x1e root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x07 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x20 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x08 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x03 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x09 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x1e root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0A root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x0a root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0B root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x02 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0C root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x0a root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0D root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x02 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0E root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x03 ================================================================================================================================================== WORKING CASE - INTERNAL TIMING - PATTERN ENABLED AND THEN DISABLED ================================================================================================================================================== root@mmt:~# i2cdump -y -f 1 0x0C No size specified (using byte-data access) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: 18 00 00 ab 8a 00 78 00 00 00 00 00 05 00 00 00 ?..??.x.....?... 10: 00 00 0a 10 00 00 fe 5e a1 a5 00 00 00 00 00 00 ..??..?^??...... 20: 00 00 25 00 00 00 00 00 00 24 00 a8 00 00 00 00 ..%......$.?.... 30: 03 10 00 00 00 00 08 34 00 0a 20 21 00 00 f0 00 ??....?4.? !..?. 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 50: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ............... 60: 00 00 00 00 10 04 0e 03 00 20 00 00 00 00 00 00 ....????. ...... 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ c0: 00 00 80 00 68 08 00 00 40 00 00 00 00 00 00 00 ..?.h?..@....... d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ f0: 5f 55 42 39 32 31 00 00 00 00 00 00 00 00 00 00 _UB921.......... root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x03 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x08 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x04 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x48 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x05 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x53 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x06 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x1e root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x07 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x20 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x08 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x03 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x09 root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x1e root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0A root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x0a root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0B root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x02 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0C root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x0a root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0D root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x02 root@mmt:~# i2cset -f -y 1 0x0C 0x66 0x0E root@mmt:~# i2cget -f -y 1 0x0C 0x67 0x03
Hi Pradeep,
I have checked the register dump, there's nothing wrong. The internal timing should be turned off when you turn off the pattern generator. Could you check:
1. The pulse width should has restriction as blow. Reg. 0x03 on 921 says the control signal filter is disabled, so DS and HS has no restriction, but VS pulse width should be more than 130 clock cycles. You should also check Reg.0x03 bit4 on 948 to check the control signal filter and restrictions. Could you show me your DE, HS and VS timing?
2. If the VS timing meets the requirement but it still doesn't work, could you check the output of the LVDS? Could you see if there's nothing output or just failed to display?
Best regards,
Cera
Hello Pradeep,
The timing looks fine for fpd-link parts.
The other thing, does the LVDS to HDMI adapter require HDCP? 921 is UB part, so it can't give out HDCP, which may cause no output on adapter.
Best regards,
Cera
Hi Pradeep,
Here's the summary of the issue, if there's something I left out, please fill in, thanks.
Issue: J6 Entry - 921 - 948 - LVDS to HDMI adapter - display doesn't work, black screen
Work around:
√ Pattern generator with internal timing - 921 - 948 - adapter - display
x Pattern generator with external timing - 921 - 948 - adapter - display
x Different pattern with external timing
Suspect control timing is wrong:
√ Checked HS, VS, DE, they all larger than 130 pclk
√ J6 Entry - 921 - 948 - display (from vendor): prove the timing works properly on the display
( This is from your description: Actual display unit with TFT from vendor ==> On this the above timings are working proper. What's the difference between this setup and the one that doesn't work?)
Suspect the adapter's fault:
√ J6Entry variant - 921 - 948 - adapter - display
(With same serializer 921 on J6Entry variant, and same adapter , we get the output on monitor, What's the difference between this setup and the one that doesn't work?)
√ Checked the HDCP, no HDCP required from the adapter
Could you check the following things:
1. Set the pattern generator to the same timing with the external timing. You can go to indirect pattern generator register to set the timing, for more details, please refer to application note: http://www.ti.com/lit/an/snla132c/snla132c.pdf. If it works, we can thoroughly exclude the timing's fault.
2. What's the specific setup you mentioned in your previous mail?
a. Actual display unit with TFT from vendor ==> On this the above timings are working proper. Is this: J6 Entry - 921 - 948 - (LVDS) display (from vendor)? The difference is there's no LVDS - HDMI adapter and the display is LVDS input?
b. With same serializer 921 on J6Entry variant, and same adapter , we get the output on monitor. Is this: J6Entry variant - 921 - 948 - adapter - display? What's the difference between this setup and the one that doesn't work?
c. The LVDS output from 948 is correct ( the LVDS displays properly) but there's no signal output from the adapter? All the HDMI data output is 000000?
Best regards,
Cera